Computer system including CPU or peripheral bridge to communicate serial bits of peripheral component interconnect bus transaction and low voltage differential signal channel to convey the serial bits
DCFirst Claim
1. A computer, comprising:
- a connector that can be configured to couple to a console;
an integrated central processing unit and graphics subsystem in a single chip;
a Low Voltage Differential Signal (LVDS) channel directly extending from the integrated central processing unit and graphics subsystem to convey encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in a serial bit stream, wherein the LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction; and
a serial bit channel that couples to the connector, wherein the serial bit channel is adapted to transmit data packets in accordance with a Universal Serial Bus (USB) protocol;
wherein the integrated central processing unit and graphics subsystem outputs digital video display signals.
1 Assignment
Litigations
1 Petition
Accused Products
Abstract
A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.
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Citations
17 Claims
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1. A computer, comprising:
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a connector that can be configured to couple to a console; an integrated central processing unit and graphics subsystem in a single chip; a Low Voltage Differential Signal (LVDS) channel directly extending from the integrated central processing unit and graphics subsystem to convey encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in a serial bit stream, wherein the LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction; and a serial bit channel that couples to the connector, wherein the serial bit channel is adapted to transmit data packets in accordance with a Universal Serial Bus (USB) protocol; wherein the integrated central processing unit and graphics subsystem outputs digital video display signals. - View Dependent Claims (2, 3, 4, 5)
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6. A computer, comprising:
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an integrated central processing unit and graphics subsystem in a single chip; a first Low Voltage Differential Signal (LVDS) channel directly extending from the integrated central processing unit and graphics subsystem, wherein the first LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction; a system memory directly coupled to the integrated central processing unit and graphics subsystem; and a graphics memory directly coupled to the integrated central processing unit and graphics subsystem; wherein the integrated central processing unit and graphics subsystem in a single chip directly conveys a serial bit stream of digital video information to a third differential signal channel. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A computer, comprising:
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a central processing unit directly connected to a Low Voltage Differential Signal (LVDS) channel comprising at least two sets of unidirectional, differential signal pairs transmitting data in opposite directions; a graphics controller coupled to the central processing unit to convey digital video information through a second differential signal channel conveying Transition Minimized Differential Signaling (TDMS) signals; and a system memory directly connected to the central processing unit. - View Dependent Claims (13)
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14. A computer, comprising:
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an integrated central processing unit and graphics subsystem in a single chip directly connected to a first Low Voltage Differential Signal (LVDS) channel wherein the first LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction; the integrated central processing unit and graphics subsystem directly connected to a second differential signal channel conveying Transition Minimized Differential Signaling (TDMS) digital video display signals. - View Dependent Claims (15, 16, 17)
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Specification