High density, low jitter, synchronous USB expansion

• US 8,626,980 B2
• Filed: 05/20/2010
• Issued: 01/07/2014
• Est. Priority Date: 05/20/2009
• Status: Expired due to Fees

• Current Assignee: ChronoLogic Pty., Ltd.
• Original Assignee: ChronoLogic Pty., Ltd.
• Inventors: Foster, Peter Graham
• Primary Examiner(s): STIGLIC, RYAN M
• Application Number:
  US13/320,334
• Publication Number:
  US 20120059964A1
• Time in Patent Office: 1,328 Days
• Field of Search: 710/300
• US Class Current: 710/315
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 11/3027 where the computing system component is a bus
• CPC Class Codes: G06F 13/10 Program control for peripheral devices G06F13/14 - G06F13/42 take precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/405 where the bridge performs a synchronising function
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2213/0042 Universal serial bus [USB]
• CPC Class Codes: H04L 7/04 Speed or phase control by synchronisation signals H04L7/0075 takes precedence
• CPC Class Codes: H04L 7/08 the synchronisation signals recurring cyclically

Abstract

A method of providing high density expansion of a USB network, the method comprising: attaching a plurality of USB hubs to adjacent slots in a PXI instrumentation chassis; configuring one of the USB hubs as a primary USB Hub; connecting an upstream port of the primary USB Hub to a USB network; configuring a first downstream port of the primary USB Hub to communicate across a first PXI Local Bus to a first adjacent USB Hub of the USB Hubs other than the primary USB Hub, the first adjacent USB Hub being adjacent to the primary USB Hub; configuring a plurality of other downstream ports of the primary USB Hub to provide expansion of the primary USB Hub; connecting an upstream port of the first adjacent USB Hub to the first PXI Local Bus, wherein the first PXI Local Bus is in the direction of the primary USB Hub; configuring a first downstream port of the first adjacent USB Hub to communicate across a second PXI Local Bus to a second adjacent USB Hub of the USB Hubs other than the primary USB Hub, the second adjacent USB Hub being adjacent to the first adjacent USB Hub; configuring a plurality of other downstream ports of the first adjacent USB Hub to provide expansion of the first adjacent USB Hub; and configuring any other of the USB hubs and the first adjacent USB Hub in like manner.

Claims

1. A method of providing expansion of a USB network, the method comprising:

attaching a plurality of USB hubs to adjacent slots in a PXI instrumentation chassis;

configuring one of said USB hubs as a primary USB Hub;

connecting an upstream port of said primary USB Hub to a USB network;

configuring a first downstream port of said primary USB Hub to communicate across a first PXI Local Bus to a first adjacent USB Hub of said plurality of USB Hubs other than said primary USB Hub, said first adjacent USB Hub being adjacent to said primary USB Hub;

configuring a plurality of other downstream ports of said primary USB Hub to provide expansion of said primary USB Hub;

connecting an upstream port of said first adjacent USB Hub to said first PXI Local Bus, wherein said first PXI Local Bus is in the direction of said primary USB Hub; and

configuring a plurality of other downstream ports of said first adjacent USB Hub to provide expansion of the first adjacent USB Hub.

2. A method as claimed in claim 1, wherein there are three or more USB hubs attached to adjacent slots in the PXI instrumentation chassis, the method further comprising:

configuring a first downstream port of said first adjacent USB Hub to communicate across a second PXI Local Bus to a second adjacent USB Hub of said plurality of USB Hubs other than said primary USB Hub, said second adjacent USB Hub being adjacent to said first adjacent USB Hub; and

configuring any other of said USB hubs in a like manner.

3. A method as claimed in claim 1, including providing a USB Host Controller of said USB network in or on said PXI instrumentation chassis.

4. A method as claimed in claim 3, wherein said primary USB hub includes said USB Host Controller.

5. A method as claimed claim 1, wherein said downstream ports of said plurality of USB Hubs utilise differential signalling across said plurality of PXI Local Buses spanning adjacent said USB Hubs.

6. A method as claimed in claim 1, including deserializing said downstream ports of said plurality of USB Hubs into a plurality of lower speed signal channels for transmission across links of said PXI Local Bus and re-serializing said downstream ports of each of said plurality of USB Hubs at said upstream port of another of said plurality of USB Hubs adjacent to said respective USB Hub.

7. A method as claimed in claim 1, further comprising:

configuring said USB Hubs attached to adjacent slots in the PXI instrumentation chassis to receive clocking signals from a PXI Star Trigger Bus via backplane connectors of the PXI instrumentation chassis; and

synchronising respective local clocks of the USB Hubs to said clocking signals provided by the PXI Star Trigger Bus.

8. A method as claimed in claim 7, further comprising:

attaching a plurality of USB devices at a plurality of points within the USB network;

clocking USB Hub Functions within each of said USB Hubs with said local clocks;

wherein a constant phase relationship is maintained between USB data signals and said USB Hub clocking at each level of said network.

9. A method as claimed in claim 8, wherein there is substantially no integer relationship between respective clock rates of said USB Hubs and a clock rate of said USB Host Controller.

10. A method as claimed claim 1, further comprising

attaching a USB Host Controller with a local clock to the PXI instrumentation chassis;

synchronising the local clock of the USB Host Controller to a PXI Trigger Bus or PXI Star Trigger Bus of the PXI instrumentation chassis;

synchronising a notion of real time of the USB Host Controller to predefined event signals derived from the PXI Trigger Bus or PXI Star Trigger Bus; and

synchronising a plurality of USB devices at respective attachment points within the USB network to a timebase and the notion of real time of the USB Host Controller.

11. A method as claimed in claim 10, wherein synchronisation of said notion of real time of said USB Host Controller includes phase compensation for USB signal propagation time.

12. An apparatus for providing expansion of a USB network, comprising:

a PXI or PXI-express form factor card containing USB hub circuitry, the USB hub circuitry including;

an upstream port for receiving USB signals from either a first PXI Local Bus or a front panel connection of a USB Hub;

a downstream USB port for expanding a USB network across a second PXI Local Bus; and

one or more additional downstream USB ports for expanding said USB network.

13. An apparatus as claimed in claim 12, further comprising a USB Host Controller, wherein said USB Host Controller is connected to an upstream port of said USB hub circuitry.

14. An apparatus as claimed in claim 13, wherein said USB hub circuitry is clocked by a local clock that has been synchronized to a timebase of the USB Host Controller.

15. An apparatus as claimed in claim 12, wherein:

the PXI or PXI-express form factor card is attached to a PXI backplane.

16. An apparatus as claimed in claim 13, wherein there is substantially no integer relationship between a clock rate of said USB Hub circuitry and a clock rate of said USB Host Controller.

17. A system comprising a PXI instrumentation chassis and a plurality of apparatus as claimed in claim 12 attached to adjacent slots in the PXI instrumentation chassis.