Data processing device

• US 8,627,046 B2
• Filed: 05/23/2011
• Issued: 01/07/2014
• Est. Priority Date: 09/06/2002
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kondo, Hiroyuki, Ohtani, Sugako
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US13/113,511
• Publication Number:
  US 20110238958A1
• Time in Patent Office: 960 Days
• Field of Search: None
• US Class Current: 712/221
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter

Abstract

A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.

Claims

1. A method of execution of a divide instruction for a data processor, comprising the steps of:

determining whether a dividend instructed in the divide instruction is a signed form number or an unsigned form number based on the divide instruction;

determining an uppermost bit location, which has a first value when the dividend is unsigned data or when the dividend is signed data and a sign of the dividend data is positive, and which has a second value when the dividend is signed data and the sign of the dividend data is negative;

determining a data size of the dividend during an execution of the divide instruction based on the determined uppermost bit location in the dividend; and

executing a divide calculation based on the divide instruction,

wherein a calculation cycle count of the divide calculation is determined depending on the data size of the dividend.

3. The method of claim 1, wherein the data size of the dividend is determined based on information indicating a size upper limit value of the dividend.

2. A method of execution of a divide instruction for a data processor, comprising the steps of:

decoding the divide instruction;

determining a data size of a dividend instructed in the divide instruction during an execution of the divide instruction; and

executing a divide calculation based on a decode result of the divide instruction,

wherein a calculation cycle count of the divide calculation is determined depending on the data size of the dividend,

wherein the divide instruction contains information indicating whether the dividend is the signed form number or the unsigned form number, and

wherein the data size of the dividend is determined based on the information in the divide instruction.

4. The method of claim 2, wherein the data size of the dividend is determined based on information indicating a size upper limit value of the dividend.