Cyclic redundancy check circuit and semiconductor device having the cyclic redundancy check circuit

• US 8,627,170 B2
• Filed: 04/27/2010
• Issued: 01/07/2014
• Est. Priority Date: 09/21/2005
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ito, Masafumi, Atsumi, Tomoaki
• Primary Examiner(s): Lamarre, Guy
• Application Number:
  US12/768,217
• Publication Number:
  US 20100205519A1
• Time in Patent Office: 1,351 Days
• Field of Search: 714/758, 714/800, 714/801, 714/802, 714/803, 714/804, 702/189
• US Class Current: 714/758
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H04B 1/10 Means associated with receiver for limiting or suppressing noise or interference

Abstract

An object of the present invention is to provide a CRC circuit with more simple structure and low power consumption. The CRC circuit includes a first shift register to a p-th shift register, a first EXOR to a (p−1)th EXOR, and a switching circuit. A data signal, a select signal, and an output of a last stage of the p-th shift register are inputted to the switching circuit, and the switching circuit switches a first signal or a second signal in response to the select signal to be outputted.

Claims

1. A semiconductor device comprising:

an antenna; and

a circuit portion configured to transmit a signal to the antenna and to receive a signal from the antenna, the circuit portion comprising a cyclic redundancy check circuit and a memory circuit, the memory circuit comprising;

a first transistor;

a first invertor comprising a second transistor and a third transistor, and a second invertor comprising a fourth transistor and a fifth transistor, each of the first invertor and the second invertor being electrically connected to the first transistor; and

a sixth transistor electrically connected to the first invertor and the second invertor,

wherein at least one of the first to sixth transistors comprises a semiconductor layer comprising a channel forming region, and wherein the channel forming region comprises a metal oxide semiconductor.

2. The semiconductor device according to claim 1, wherein the memory circuit is an SRAM.

3. The semiconductor device according to claim 1, wherein the cyclic redundancy check circuit comprises:

a first shift register to a p-th (p is a natural number greater than

     1) shift register which each have one stage or a plurality of stages connected in cascade, and in which an inputted signal is delayed and then outputted from the one stage or the plurality of stages, and in which the output from the one stage or the plurality of stages is performed in synchronization with a clock signal;

a first exclusive OR circuit to a (p−

1)th exclusive OR circuit each calculating an exclusive OR of two inputted signals; and

a switching circuit to which a data signal, a select signal, and an output of a last stage of the p-th shift register are inputted, and which switches one of a first signal or a second signal to be outputted in response to the select signal,

wherein an output of the switching circuit is inputted to a first stage of the first shift register,

wherein an output of a last stage of an r-th (r is a natural number smaller than p) shift register, and the output of the switching circuit are inputted to an r-th exclusive OR circuit, and an output of the r-th exclusive OR circuit is inputted to a first stage of a (r+1)th shift register,

wherein the first signal is an exclusive OR of the data signal and the output of the last stage of the p-th shift register, and

wherein the second signal is a logical value of “

0”

.

4. A semiconductor device comprising:

an antenna; and

a circuit portion configured to transmit a signal to the antenna and to receive a signal from the antenna, the circuit portion comprising a power supply circuit, a demodulation circuit, a modulation circuit, a cyclic redundancy check circuit and a memory circuit, the memory circuit comprising;

a first transistor;

a first invertor comprising a second transistor and a third transistor, and a second invertor comprising a fourth transistor and a fifth transistor, each of the first invertor and the second invertor being electrically connected to the first transistor; and

a sixth transistor electrically connected to the first invertor and the second invertor,

wherein at least one of the first to sixth transistors comprises a semiconductor layer comprising a channel forming region, and wherein the channel forming region comprises a metal oxide semiconductor.

5. The semiconductor device according to claim 4, wherein the memory circuit is an SRAM.

6. The semiconductor device according to claim 4, wherein the cyclic redundancy check circuit comprises:

a first shift register to a p-th (p is a natural number greater than

     1) shift register which each have one stage or a plurality of stages connected in cascade, and in which an inputted signal is delayed and then outputted from the one stage or the plurality of stages, and in which the output from the one stage or the plurality of stages is performed in synchronization with a clock signal;

a first exclusive OR circuit to a (p−

1)th exclusive OR circuit each calculating an exclusive OR of two inputted signals; and

a switching circuit to which a data signal, a select signal, and an output of a last stage of the p-th shift register are inputted, and which switches one of a first signal or a second signal to be outputted in response to the select signal,

wherein an output of the switching circuit is inputted to a first stage of the first shift register,

wherein an output of a last stage of an r-th (r is a natural number smaller than p) shift register, and the output of the switching circuit are inputted to an r-th exclusive OR circuit, and an output of the r-th exclusive OR circuit is inputted to a first stage of a (r+1)th shift register,

wherein the first signal is an exclusive OR of the data signal and the output of the last stage of the p-th shift register, and

wherein the second signal is a logical value of “

0”

.

7. A semiconductor device comprising:

an antenna configured to receive a carrier wave;

a pass-band filter configured to remove a noise from the carrier wave;

a demodulation circuit configured to demodulate the carrier wave passed through the pass-band filter;

a power supply circuit configured to generate a direct voltage by using the carrier wave passed through the pass-band filter;

a code extraction circuit configured to extract a code of a signal of the carrier wave demodulated by the demodulation circuit;

a code determination circuit configured to analyze the code from the code extraction circuit;

a cyclic redundancy check circuit configured to calculate a CRC code corresponding to a transmitting data signal;

a control circuit configured to add the CRC code to the transmitting data signal;

a memory circuit configured to output a stored unique identifier to the control circuit, the memory circuit comprising;

a first transistor;

a first invertor comprising a second transistor and a third transistor, and a second invertor comprising a fourth transistor and a fifth transistor, each of the first invertor and the second invertor being electrically connected to the first transistor; and

a sixth transistor electrically connected to the first invertor and the second invertor, and

a modulation circuit configured to load-modulate the carrier wave in accordance with a signal from the control circuit,

wherein at least one of the first to sixth transistors comprises a semiconductor layer comprising a channel forming region, and wherein the channel forming region comprises a metal oxide semiconductor.

8. The semiconductor device according to claim 7, wherein the memory circuit is an SRAM.

9. The semiconductor device according to claim 7, wherein the cyclic redundancy check circuit comprises:

a first shift register to a p-th (p is a natural number greater than

     1) shift register which each have one stage or a plurality of stages connected in cascade, and in which an inputted signal is delayed and then outputted from the one stage or the plurality of stages, and in which the output from the one stage or the plurality of stages is performed in synchronization with a clock signal;

a first exclusive OR circuit to a (p−

1)th exclusive OR circuit each calculating an exclusive OR of two inputted signals; and

a switching circuit to which a data signal, a select signal, and an output of a last stage of the p-th shift register are inputted, and which switches one of a first signal or a second signal to be outputted in response to the select signal,

wherein an output of the switching circuit is inputted to a first stage of the first shift register,

wherein an output of a last stage of an r-th (r is a natural number smaller than p) shift register, and the output of the switching circuit are inputted to an r-th exclusive OR circuit, and an output of the r-th exclusive OR circuit is inputted to a first stage of a (r+1)th shift register,

wherein the first signal is an exclusive OR of the data signal and the output of the last stage of the p-th shift register, and

wherein the second signal is a logical value of “

0”

.