Structure and method to form EDRAM on SOI substrate

• US 8,629,017 B2
• Filed: 03/12/2012
• Issued: 01/14/2014
• Est. Priority Date: 05/07/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Pei, Chengwen, Cheng, Kangguo, Ho, Herbert L., Iyer, Subramanian S., Kim, Byeong Y., Wang, Geng, Zhu, Huilong
• Primary Examiner(s): ARORA, AJAY
• Application Number:
  US13/417,900
• Publication Number:
  US 20120171827A1
• Time in Patent Office: 673 Days
• Field of Search: 438/243
• US Class Current: 438/243
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.

Claims

1. A method for forming a memory device comprising:

providing a semiconductor substrate;

forming a trench capacitor in the semiconductor substrate, the trench capacitor including an inner electrode comprised of a conductive fill material within a trench;

forming a buried dielectric layer on the semiconductor substrate and on the trench capacitor;

forming a first stud in the buried dielectric layer in electrical communication with the conductive material that is present within the trench and a second stud in the buried dielectric layer in electrical communication with the semiconductor substrate;

forming a semiconductor layer on the buried dielectric layer; and

forming a semiconductor device atop the semiconductor layer over the trench, the semiconductor device comprising a gate structure, a source region and a drain region, wherein at least the gate structure, the source region and the drain region of the semiconductor device is formed after the trench capacitor, and the drain region is in electrical communication with the first stud, wherein the gate structure of the semiconductor device is substantially centrally positioned over the trench capacitor.

2. The method of claim 1, wherein forming the trench that contains the trench capacitor comprises forming a pad stack atop the semiconductor substrate including a first pad dielectric layer on the semiconductor substrate and a second pad dielectric layer on the first pad dielectric layer;

forming a photoresist mask atop the pad stack;

etching the pad stack selective to the photoresist mask; and

etching the semiconductor substrate to provide the trench using a remaining portion of the pad stack as an etch mask.

3. The method of claim 2, further comprising forming a node dielectric on the sidewall of the trench prior to forming the inner electrode of the trench capacitor.

4. The method of claim 1, wherein the forming of the conductive material within the trench includes chemical vapor deposition or physical deposition of the conductive material within the trench followed by planarization.

5. The method of claim 1, wherein at least one of the buried dielectric layer and the semiconductor layer are formed by deposition or layer transfer.

6. The method of claim 1, wherein the forming of the semiconductor device atop the semiconductor layer comprises forming a gate dielectric and a gate conductor of the gate structure followed by ion implantation of a p-type or n-type dopant to provide the source region and the drain region of the semiconductor device.

7. A method for forming a memory device comprising:

providing a semiconductor substrate having at least one trench capacitor formed therein;

forming a buried dielectric layer on the semiconductor substrate;

forming at least one semiconductor device atop the buried dielectric layer comprising a gate structure, a source region and a drain region, wherein at least the gate structure, the source region and the drain region of the semiconductor device is formed after the trench capacitor, wherein the gate structure of the semiconductor device is substantially centrally positioned over the trench capacitor; and

forming a first contact through the buried dielectric layer in electrical contact with the semiconductor substrate and a second contact from the drain region for each of the at least one semiconductor device through the buried dielectric layer into electrical contact to an inner electrode for each of the at least one trench capacitor.

8. The method of claim 7, wherein at least one of the first contact and the second contact comprises a metal.

9. The method of claim 7, wherein the memory device does not include an arsenic doped silicon glass strap region between the semiconductor device and the trench capacitor.

10. The method of claim 7, wherein the at least one trench capacitor includes an outer electrode comprised of a doped sidewall of a trench that contains the at least one trench capacitor, a node dielectric layer that is present on the doped sidewall of the trench, and an inner electrode provided by a conductive fill material.

11. The method of claim 7, wherein forming the buried dielectric layer comprises deposition or layer transfer.

12. The method of claim 7 wherein the forming of the semiconductor device comprises forming a semiconductor layer on the buried dielectric layer and forming a gate dielectric and a gate conductor of the gate structure on the semiconductor layer followed by ion implantation of a p-type or n-type dopant to provide the source region and the drain region of the semiconductor device.

13. The method of claim 7, wherein the forming of the semiconductor layer comprises deposition or layer transfer.

14. The method of claim 7, wherein the at least one trench capacitor includes a first trench capacitor and a second trench capacitor, wherein the first trench capacitor is formed within a first trench and the second trench capacitor is formed within a second trench, wherein a first width of the first trench is different than a second width of the second trench.

15. The method of claim 14, wherein the first width ranges from 30 nm to 180 nm, and a second width ranges from 150 nm to 300 nm.

16. A method for forming a memory device comprising:

providing a semiconductor substrate;

forming a trench capacitor in the semiconductor substrate, the trench capacitor including an inner electrode comprised of a conductive fill material within a trench;

forming a buried dielectric layer on the semiconductor substrate and on the trench capacitor;

forming a first stud in the buried dielectric layer in electrical communication with the conductive material that is present within the trench and a second stud in the buried dielectric layer in electrical communication with the semiconductor substrate;

forming a semiconductor layer on the buried dielectric layer; and

forming a semiconductor device atop the semiconductor layer over the trench, the semiconductor device comprising a gate structure, a source region and a drain region, wherein the gate structure of the semiconductor device is substantially centrally positioned over the trench capacitor.

17. The method of claim 16, wherein forming the trench that contains the trench capacitor comprises forming a pad stack atop the semiconductor substrate including a first pad dielectric layer on the semiconductor substrate and a second pad dielectric layer on the first pad dielectric layer;

forming a photoresist mask atop the pad stack;

etching the pad stack selective to the photoresist mask; and

etching the semiconductor substrate to provide the trench using a remaining portion of the pad stack as an etch mask.

18. The method of claim 16, further comprising forming a node dielectric on the sidewall of the trench prior to forming the inner electrode of the trench capacitor.

19. The method of claim 16, wherein the forming of the conductive material within the trench includes chemical vapor deposition or physical deposition of the conductive material within the trench followed by planarization.

20. The method of claim 16, wherein the forming of the semiconductor device atop the semiconductor layer comprises forming a gate dielectric and a gate conductor of the gate structure followed by ion implantation of a p-type or n-type dopant to provide the source region and the drain region of the semiconductor device.