Method of forming self aligned contacts for a power MOSFET

• US 8,629,019 B2
• Filed: 09/24/2002
• Issued: 01/14/2014
• Est. Priority Date: 09/24/2002
• Status: Expired due to Term

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Xu, Robert Q., Korec, Jacek
• Primary Examiner(s): CHEN, JACK S J
• Application Number:
  US10/254,385
• Publication Number:
  US 20040058481A1
• Time in Patent Office: 4,130 Days
• Field of Search: 438/270, 438/268, 438/589, 438/639, 438/275, 257/E21.585
• US Class Current: 438/270
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for providing self aligned contacts for a trench power MOSFET is disclosed. The method includes, etching trenches in a substrate through a mask of silicon nitride deposited on an oxide layer, forming a gate oxide layer on the walls of the trenches, applying polysilicon to fill the trenches and to cover the surface of the mask of silicon nitride, removing the polysilicon from the surface of the mask of silicon nitride and applying a photoresist mask to cover a location of a gate bus. The method further includes recessing polysilicon plugs formed in trenches that are located in the active area to form recesses above the polysilicon plugs, filling recesses formed above the polysilicon plugs formed in trenches that are located in the active area with an insulator, applying a fourth photo resist mask to define contact windows that are opened in the nitride layer, and selectively etching the silicon nitride film and leaving flat surfaced oxide buttons covering the trenches that are located in the active area. Moreover, electric contact trenches are defined using self-aligned spacer operations, and a fifth photo resist mask is applied to pattern metal contacts that reach the semiconductor device active areas.

Claims

1. A method for providing self aligned contacts in a semiconductor device having an active area and a gate bus area comprising:

forming an oxide layer on a substrate of said semiconductor device;

forming a hard mask of silicon nitride on said oxide layer;

etching said hard mask of silicon nitride to form trenches in said active area and said gate bus area in said substrate wherein said hard mask of silicon nitride is deposited on said oxide layer;

forming a gate oxide layer on walls of said trenches;

applying polysilicon to fill said trenches and to cover the surface of said hard mask of silicon nitride;

removing said polysilicon from the surface of said hard mask of silicon nitride;

forming and recessing polysilicon plugs in trenches that are located in said active area to form recesses above said polysilicon plugs while leaving the polysilicon coplanar with the hard mask of silicon nitride on the gate bus area; and

selectively etching said hard mask of silicon nitride and forming flat, wholly planar surfaced oxide buttons to cover said trenches that are located in said active area.

2. The method of claim 1, further comprising:

defining contact windows in the hard mask of silicon nitride;

forming electric contact trenches using self aligned spacer operations using said contact windows; and

forming metal contacts in said electric contact trenches.

3. The method of claim 2, further comprising forming and isolating a polysilicon material located in said active area of a semiconductor device and providing access to the top of a polysilicon plug located in said gate bus area of said semiconductor device.

4. The method of claim 3, wherein said removing said polysilicon from the surface of the hard mask of silicon nitride comprises a CMP (chemo mechanical polishing method) operation.

5. The method of claim 4, further comprising distinguishing between the active area of said semiconductor device and the gate bus area.

6. The method of claim 5, wherein said polysilicon plugs have a height in said gate bus area that is coincident with the surface of the hard mask of silicon nitride.

7. The method of claim 2, wherein said insulator is etched selectively with regard to the hard mask of silicon nitride.

8. The method of claim 7, wherein said insulator comprises oxide or BPSG.

9. The method of claim 2, further comprising forming a metal portion that comprises a gate bus and making electrical contact between a polysilicon plug and said metal portion that comprises said gate bus.

10. The method of claim 3, wherein said etching trenches in a substrate comprises etching a wide trench.

11. The method of claim 10, wherein said wide trench is filled with a polycrystalline film having a semiconductor device that is integrated with a transistor formed in said active area formed therein.

12. The method of claim 2, further comprising:

creating oxide spacers along the walls of said contact windows;

etching the substrate surface to form a contact trench in a RIE operation; and

forming a contact implant at the bottom of said contact trench to increase the dopant concentration in a body well at a contact interface.

13. A method for providing self aligned contacts in a semiconductor device having an active area and a gate bus area comprising:

forming an oxide layer on a substrate of said semiconductor device;

forming a hard mask of silicon nitride on said oxide layer;

etching said hard mask of silicon nitride to form trenches in said active area and said gate bus area in said substrate wherein said hard mask of silicon nitride is deposited on said oxide layer;

forming a gate oxide layer on walls of said trenches;

applying polysilicon to fill said trenches and to cover the surface of said hard mask of silicon nitride;

removing said polysilicon from the surface of said hard mask of silicon nitride;

forming and recessing polysilicon plugs in trenches that are located in said active area to form recesses above the polysilicon plugs while leaving the polysilicon coplanar with the hard mask of silicon nitride on the gate bus area and filling recesses formed above said polysilicon plugs, that are formed in said trenches located in said active area, with an insulator; and

etching said silicon nitride film and forming flat, wholly planar surfaced oxide buttons to cover the trenches that are located in said active area.

14. The method of claim 13, further comprising:

defining contact windows in said hard mask of silicon nitride;

forming electric contact trenches using said contact windows; and

forming metal contacts in said electric contact trenches.

15. The method of claim 14, further comprising forming and isolating a polysilicon material located in said active area and providing access to the top of a polysilicon plug located in a said gate bus area.

16. The method of claim 15, wherein said removing said polysilicon from the surface of the hard mask of silicon nitride comprises a CMP (chemo mechanical polishing method) operation.

17. The method of claim 16, further comprising distinguishing between said active area and said gate bus area.

18. The method of claim 17, wherein said polysilicon plugs located in said gate bus area have a height that is coincident with the surface of the hard mask of silicon nitride.

19. The method of claim 14, wherein said insulator is selectively etched.

20. The method of claim 19, wherein said insulator comprises oxide or BPSG.

21. The method of claim 14, further comprising making electrical contact between a polysilicon plug and the said gate bus area.

22. The method of claim 15, wherein a wide trench is etched in said substrate.

23. The method of claim 22, wherein said wide trench is filled with a polycrystalline film having a semiconductor device that is integrated with a transistor formed in said active area and which is accessible at a surface of said substrate.

24. The method of claim 14, further comprising:

forming oxide spacers along the walls of said contact windows;

etching the substrate surface to form a contact trench in a RIE operation; and

forming a contact implant at the bottom of said contact trench to increase the dopant concentration in a body well at a contact interface.

25. A method for providing self aligned contacts in a semiconductor device having an active area and a gate bus area comprising:

forming an oxide layer on a substrate of said semiconductor device;

forming a hard mask of silicon nitride on said oxide layer;

etching said hard mask to form trenches in said active area and said gate bus area in said substrate;

forming a gate oxide layer on walls of said trenches;

applying polysilicon to fill said trenches;

removing said polysilicon from the surface of said hard mask;

forming and recessing polysilicon plugs in trenches that are located in said active area to form recesses above the polysilicon plugs while leaving the polysilicon coplanar with the hard mask of silicon nitride on the gate bus area and filling recesses formed above said polysilicon plugs, that are formed in said trenches located in said active area, with an insulator; and

forming flat, wholly planar surfaced oxide buttons above the trenches that are located in said active area.

26. The method of claim 25, further comprising:

defining contact windows in said hard mask;

forming electric contact trenches for contacting active regions using said contact windows; and

forming metal contacts in said electric contact trenches.

27. The method of claim 26, further comprising forming and isolating a polysilicon material located in said active area and providing access to the top of a polysilicon plug located in said gate bus area.

28. The method of claim 27, further comprising distinguishing between said active area and said gate bus area.

29. The method of claim 28, wherein said polysilicon plugs have a height that is coincident with the surface of said hard mask.

30. The method of claim 25, wherein said insulator comprises oxide or BPSG.

31. The method of claim 30, wherein a wide trench is etched in said substrate.

32. The method of claim 31, wherein said wide trench is filled with a polycrystalline film having a semiconductor device that is integrated with a transistor formed in said active area and which is accessible at a surface of said substrate.