Method for stacking semiconductor dies

• US 8,629,042 B2
• Filed: 01/23/2013
• Issued: 01/14/2014
• Est. Priority Date: 12/08/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Ku-Feng, Wu, Weng-Jin, Chiou, Wen-Chih, Yu, Chen-Hua
• Primary Examiner(s): SMITH, BRADLEY
• Application Number:
  US13/748,509
• Publication Number:
  US 20130137222A1
• Time in Patent Office: 356 Days
• Field of Search: 438/459, 438/460, 438/691
• US Class Current: 438/460
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01019 : Potassium [K]

Abstract

A system and method for stacking semiconductor dies is disclosed. A preferred embodiment comprises forming through-silicon vias through the wafer, protecting a rim edge of the wafer, and then removing the unprotected portions so that the rim edge has a greater thickness than the thinned wafer. This thickness helps the fragile wafer survive further transport and process steps. The rim edge is then preferably removed during singulation of the individual dies from the wafer.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

placing a wafer into a chuck, the wafer comprising a first side, a second side opposite the first side, and a conductive plug extending at least partially through the wafer, the chuck covering an edge of the wafer;

transferring a pattern of the chuck to the first side of the wafer, the transferring the pattern of the chuck exposing the conductive plug and forming a recess within the wafer; and

separating a first portion of the wafer with the recess from a second portion of the wafer without the recess.

2. The method of claim 1, wherein the transferring the pattern of the chuck is performed at least in part using an etching process.

3. The method of claim 2, wherein the etching process further comprises:

a first bulk etch; and

a second etch.

4. The method of claim 3, wherein the etching process further comprises an overetch to remove material of the wafer such that the conductive plug extends away from the wafer.

5. The method of claim 1, further comprising bonding a semiconductor die to the first portion of the wafer prior to the separating the first portion of the wafer.

6. The method of claim 5, further comprising encapsulating the semiconductor die with a fill material.

7. The method of claim 1, wherein the recess has an interior edge comprising a plurality of straight lines.

8. A method of manufacturing a semiconductor device, the method comprising:

forming a scribe line separating a first region of a semiconductor substrate from a second region of a semiconductor substrate, the first region comprising a die area;

placing a first material over the second region adjacent to the scribe line and over an edge of the semiconductor substrate while leaving the first region unprotected;

removing a portion of the first region to expose conductive plugs located in the first region, the conductive plugs extending through the semiconductor substrate after the removing the portion of the first region, wherein the removing the portion of the first region thins the first region without thinning the second region; and

separating the first region from the second region along the scribe line.

9. The method of claim 8, wherein the placing the first material comprises placing a photoresist over the second region.

10. The method of claim 8, wherein the placing the first material comprises placing an adhesive tape over the second region.

11. The method of claim 8, wherein the placing the first material comprises placing the semiconductor substrate into a chuck, a portion of the chuck overlying the second region adjacent to the scribe line.

12. The method of claim 8, wherein the separating the first region from the second region is performed at least in part using a saw blade to slice the scribe line.

13. The method of claim 8, further comprising bonding a semiconductor die to the conductive plugs prior to the separating the first region from the second region.

14. The method of claim 13, further comprising encapsulating the semiconductor die with an encapsulant prior to the separating the first region from the second region, the encapsulant covering the scribe line and in contact with the second region.

15. A method of manufacturing a semiconductor device, the method comprising:

manufacturing active devices on a first side of a substrate, the active devices being located in a first region of the substrate surrounded by a second region of the substrate;

removing portions of the substrate to form openings further into the substrate than the active devices;

protecting with a protective material an edge of the substrate, the first side of the substrate, and the second region of the substrate on a second side of the substrate from the first side, the second side of the substrate being opposite the first side of the substrate; and

thinning the second side of the substrate to expose the openings without thinning the second region, the thinning the second side of the substrate transferring a pattern of the protective material to the substrate.

16. The method of claim 15, wherein the protective material is a chuck.

17. The method of claim 15, wherein the thinning the second side of the substrate further comprises:

a bulk removal etch; and

a finishing etch.

18. The method of claim 15, wherein the protective material is a photoresist.

19. The method of claim 15, further comprising:

filling the openings with a conductive material; and

bonding a semiconductor die to the conductive material.

20. The method of claim 19, further comprising:

encapsulating the semiconductor die after the bonding the semiconductor die; and

singulating the first region from the second region after the encapsulating the semiconductor die.