Semiconductor device and manufacturing method thereof

• US 8,629,432 B2
• Filed: 01/07/2010
• Issued: 01/14/2014
• Est. Priority Date: 01/16/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sakata, Junichiro, Shimazu, Takashi, Ohara, Hiroki, Sasaki, Toshinari, Yamazaki, Shunpei
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): Harrison, Monica D
• Application Number:
  US12/683,681
• Publication Number:
  US 20100181565A1
• Time in Patent Office: 1,468 Days
• Field of Search: 257/43, 257/E29.296, 257/E21.461
• US Class Current: 257/43
• CPC Class Codes: C23C 14/086 of zinc, germanium, cadmium, indium, tin, thallium or bismuth
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02573 Conductivity type
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H04M 1/0266 for a display module assembly

Abstract

A semiconductor device including a thin film transistor which includes an oxide semiconductor layer and has high electric characteristics and reliability. Film deposition is performed using an oxide semiconductor target containing an insulator (an insulating oxide, an insulating nitride, silicon oxynitride, aluminum oxynitride, or the like), typically SiO₂, so that the semiconductor device in which the Si-element concentration in the thickness direction of the oxide semiconductor layer has a gradient which increases in accordance with an increase in a distance from a gate electrode is realized.

Claims

1. A semiconductor device comprising:

a gate electrode over an insulating surface;

an insulating layer over the gate electrode;

a first oxide semiconductor layer over the insulating layer;

a second oxide semiconductor layer over the first oxide semiconductor layer, the second oxide semiconductor layer containing zinc and silicon, and

a source electrode and a drain electrode over the second oxide semiconductor layer;

wherein the second oxide semiconductor layer includes a depression between the source electrode and the drain electrode, and

wherein a concentration of silicon in the second oxide semiconductor layer is larger than a concentration of silicon in the first oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein the second oxide semiconductor layer is amorphous.

3. A semiconductor device comprising:

a gate electrode over an insulating surface;

an insulating layer over the gate electrode;

a first oxide semiconductor layer over the insulating layer;

a second oxide semiconductor layer over the first oxide semiconductor layer, the second oxide semiconductor layer containing zinc and SiO_x, and

a source electrode and a drain electrode over the second oxide semiconductor layer;

wherein the second oxide semiconductor layer includes a depression between the source electrode and the drain electrode, and

wherein a concentration of silicon in the second oxide semiconductor layer is larger than a concentration of silicon in the first oxide semiconductor layer.

4. The semiconductor device according to claim 3, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer contains indium.

5. The semiconductor device according to claim 3, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer contains gallium.

6. The semiconductor device according to claim 3, wherein the first oxide semiconductor layer or the second oxide semiconductor layer is formed by a sputtering method using an oxide semiconductor target containing SiO₂ at from 0.1 wt % to 10 wt % inclusive.

7. The semiconductor device according to claim 3, wherein the second oxide semiconductor layer is amorphous.

8. A semiconductor device comprising:

a first oxide semiconductor layer over an insulating surface, the first oxide semiconductor layer containing zinc and silicon;

a second oxide semiconductor layer over the first oxide semiconductor layer;

an insulating layer over the second oxide semiconductor layer; and

a gate electrode over the insulating layer,

wherein a concentration of silicon in the first oxide semiconductor layer is larger than a concentration of silicon in the second oxide semiconductor layer.

9. The semiconductor device according to claim 8, wherein the first oxide semiconductor layer is amorphous.

10. A semiconductor device comprising:

a first oxide semiconductor layer over an insulating surface, the first oxide semiconductor layer containing zinc and SiO_x;

a second oxide semiconductor layer over the first oxide semiconductor layer;

an insulating layer over the second oxide semiconductor layer; and

a gate electrode over the insulating layer,

wherein a concentration of silicon in the first oxide semiconductor layer is larger than a concentration of silicon in the second oxide semiconductor layer.

11. The semiconductor device according to claim 10, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer contains indium.

12. The semiconductor device according to claim 10, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer contains gallium.

13. The semiconductor device according to claim 10, wherein the first oxide semiconductor layer or the second oxide semiconductor layer is formed by a sputtering method using an oxide semiconductor target containing SiO₂ at from 0.1 wt % to 10 wt % inclusive.

14. The semiconductor device according to claim 10, wherein the first oxide semiconductor layer is amorphous.

15. A semiconductor device comprising:

a first oxide semiconductor layer on and in contact with an insulating surface, the first oxide semiconductor layer containing indium, gallium, zinc and silicon;

a second oxide semiconductor layer over the first oxide semiconductor layer, the second oxide semiconductor layer containing indium, gallium and zinc; and

a gate electrode adjacent to the first oxide semiconductor layer and the second oxide semiconductor layer,

wherein a concentration of silicon in the first oxide semiconductor layer is larger than a concentration of silicon in the second oxide semiconductor layer.

16. The semiconductor device according to claim 15, wherein the gate electrode is formed over the second oxide semiconductor layer.

17. The semiconductor device according to claim 15, wherein the first oxide semiconductor layer is amorphous.