Semiconductor device

• US 8,629,493 B2
• Filed: 11/26/2012
• Issued: 01/14/2014
• Est. Priority Date: 01/09/2007
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N.
• Primary Examiner(s): Parker, Kenneth
• Assistant Examiner(s): Diaz, Jose R
• Application Number:
  US13/684,610
• Publication Number:
  US 20130168762A1
• Time in Patent Office: 414 Days
• Field of Search: 257/335, 257/342, 257E29256-E29258, 257/E29.261, 257/E29.264, 257/E29.027, 257/E29.066
• US Class Current: 257/330
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02321 introduction of substances into an already existing insulating layer H01L21/02227 and subgroups take precedence
• CPC Class Codes: H01L 21/2003 characterised by the substrate
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 : Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/408 : with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/66537 : using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66666 : Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 : having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor device includes a semiconductor layer of a first conductivity type having a first surface and a second surface, a source region disposed on the first surface, a gate region disposed on the first surface adjacent the source region, and a drain region disposed on the first surface. The semiconductor device also includes a pair of charge control trenches disposed between the gate region and the drain region. Each of the pair of charge control trenches is characterized by a width and includes a first dielectric material disposed therein and a second material disposed internal to the first dielectric material. Additionally, a concentration of doping impurities present in the semiconductor layer of the first conductivity type and a distance between the pair of charge control trenches define an electrical characteristic of the semiconductor device that is independent of the width of each of the pair of charge control trenches.

Claims

1. A semiconductor device comprising a p-type semiconductor layer, the p-type semiconductor layer having formed thereon:

a first n-type semiconductor region, wherein the first n-type semiconductor region is characterized by a first thickness;

a first trench having a predetermined depth and extending into the first n-type semiconductor region, thereby defining a first interfacial region disposed between the first n-type semiconductor region and the first trench, wherein the first trench comprises;

a first dielectric material disposed in a proximal portion of the first trench and distal portion of the first trench, wherein an intentionally introduced charge is present in at least one of the first dielectric material disposed in the proximal portion of the first trench or the first interfacial region; and

a first gate material disposed interior to the first dielectric material in the proximal portion of the first trench; and

a second p-type semiconductor region, wherein the second p-type semiconductor region is characterized by a second thickness;

a second trench having a second predetermined depth and extending into the second p-type semiconductor region, thereby defining a second interfacial region disposed between the second p-type semiconductor region and the second trench, wherein the second trench comprises;

a second dielectric material disposed in a proximal portion of the second trench and distal portion of the second trench, wherein an intentionally introduced charge is provided in at least one of the second dielectric material disposed in the proximal portion of the second trench or the second interfacial region; and

a second gate material disposed interior to the second dielectric material in the proximal portion of the second trench;

wherein the first dielectric material disposed in the distal portion of the first trench and the second dielectric material disposed in the distal portion of the second trench further comprises a third dielectric material disposed interior to the first dielectric material and the second dielectric material.

2. The semiconductor device of claim 1 further comprising:

a first source region coupled to the p-type semiconductor layer;

a second source region coupled to the p-type semiconductor layer;

and a trench isolation region disposed between the first n-type semiconductor region and the second p-type semiconductor region.

3. The semiconductor device of claim 1 wherein the first dielectric material and the second dielectric material comprise a silicon oxide material.

4. The semiconductor device of claim 1 wherein the third dielectric material comprises aluminum fluoride.

5. The semiconductor device of claim 1 wherein the intentionally introduced charge comprises a net negative charge associated with a region of iodine, bromine, chromium, aluminum, or chlorine ions.

6. The semiconductor device of claim 1 wherein:

a first drain region is electrically connected to the first n-type semiconductor region by a first p-type sinker region extending to the first n-type semiconductor region; and

a second drain region is electrically connected to the second p-type semiconductor region by a second n-type sinker region extending to the second p-type semiconductor region.

7. The semiconductor device of claim 1 wherein the first n-type semiconductor region and the second p-type region are adapted to receive a first voltage.

8. A semiconductor device comprising a p-type semiconductor layer, the p-type semiconductor layer having formed thereon:

a first n-type semiconductor region, wherein the first n-type semiconductor region is characterized by a first thickness;

a first trench having a predetermined depth and extending into the first n-type semiconductor region, thereby defining a first interfacial region disposed between the first n-type semiconductor region and the first trench, wherein the first trench comprises;

a first dielectric material disposed in a proximal portion of the first trench and distal portion of the first trench, wherein an intentionally introduced charge is present in at least one of the first dielectric material disposed in the proximal portion of the first trench or the first interfacial region; and

a first gate material disposed interior to the first dielectric material in the proximal portion of the first trench; and

a second p-type semiconductor region, wherein the second p-type semiconductor region is characterized by a second thickness;

a second trench having a second predetermined depth and extending into the second p-type semiconductor region, thereby defining a second interfacial region disposed between the second p-type semiconductor region and the second trench, wherein the second trench comprises;

a second dielectric material disposed in a proximal portion of the second trench and distal portion of the second trench, wherein an intentionally introduced charge is provided in at least one of the second dielectric material disposed in the proximal portion of the second trench or the second interfacial region; and

a second gate material disposed interior to the second dielectric material in the proximal portion of the second trench;

wherein the intentionally introduced charge comprises a net positive charge associated with a region of cesium ions.

9. The semiconductor device of claim 8 wherein:

a first drain region is electrically connected to the first n-type semiconductor region by a first p-type sinker region extending to the first n-type semiconductor region; and

a second drain region is electrically connected to the second p-type semiconductor region by a second n-type sinker region extending to the second p-type semiconductor region.

10. The semiconductor device of claim 8 wherein the intentionally introduced charge comprises a net negative charge associated with a region of iodine, bromine, chromium, aluminum, or chlorine ions.

11. The semiconductor device of claim 8 further comprising:

a first source region coupled to the p-type semiconductor layer;

a second source region coupled to the p-type semiconductor layer;

and a trench isolation region disposed between the first n-type semiconductor region and the second p-type semiconductor region.

12. The semiconductor device of claim 8 wherein the first dielectric material and the second dielectric material comprise a silicon oxide material.

13. A semiconductor device comprising a p-type semiconductor layer, the p-type semiconductor layer having formed thereon:

a first n-type semiconductor region, wherein the first n-type semiconductor region is characterized by a first thickness;

a first trench having a predetermined depth and extending into the first n-type semiconductor region, thereby defining a first interfacial region disposed between the first n-type semiconductor region and the first trench, wherein the first trench comprises;

a first dielectric material disposed in a proximal portion of the first trench and distal portion of the first trench, wherein an intentionally introduced charge is present in at least one of the first dielectric material disposed in the proximal portion of the first trench or the first interfacial region; and

a first gate material disposed interior to the first dielectric material in the proximal portion of the first trench; and

a second p-type semiconductor region, wherein the second p-type semiconductor region is characterized by a second thickness;

a second trench having a second predetermined depth and extending into the second p-type semiconductor region, thereby defining a second interfacial region disposed between the second p-type semiconductor region and the second trench, wherein the second trench comprises;

a second dielectric material disposed in a proximal portion of the second trench and distal portion of the second trench, wherein an intentionally introduced charge is provided in at least one of the second dielectric material disposed in the proximal portion of the second trench or the second interfacial region; and

a second gate material disposed interior to the second dielectric material in the proximal portion of the second trench;

wherein the intentionally introduced charge is also present in the first semiconductor region and the second semiconductor region.

14. The semiconductor device of claim 13 wherein:

a first drain region is electrically connected to the first n-type semiconductor region by a first p-type sinker region extending to the first n-type semiconductor region; and

a second drain region is electrically connected to the second p-type semiconductor region by a second n-type sinker region extending to the second p-type semiconductor region.

15. The semiconductor device of claim 13 wherein the intentionally introduced charge comprises a net negative charge associated with a region of iodine, bromine, chromium, aluminum, or chlorine ions.

16. The semiconductor device of claim 13 further comprising:

a first source region coupled to the p-type semiconductor layer;

a second source region coupled to the p-type semiconductor layer;

and a trench isolation region disposed between the first n-type semiconductor region and the second p-type semiconductor region.

17. The semiconductor device of claim 13 wherein the first dielectric material and the second dielectric material comprise a silicon oxide material.