Stress-generating structure for semiconductor-on-insulator devices

• US 8,629,501 B2
• Filed: 02/10/2012
• Issued: 01/14/2014
• Est. Priority Date: 09/25/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Zhu, Huilong, Greene, Brian J., Chidambarrao, Dureseti, Freeman, Gregory G.
• Primary Examiner(s): Warren, Matthew E
• Assistant Examiner(s): CHEN, DAVID Z
• Application Number:
  US13/370,898
• Publication Number:
  US 20120139081A1
• Time in Patent Office: 704 Days
• Field of Search: 257/347, 257/E21.32, 257/E21.561, 257/E21.564, 257/E27.112
• US Class Current: 257/347
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0603 characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions isolation regions between components H01L21/76; design considerations for integrated circuits H01L27/00; geometrical design considerations for devices H01L29/0657
• CPC Class Codes: H01L 29/1025 Channel region of field-effect devices
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/84 controllable by variation of applied mechanical force, e.g. of pressure

Abstract

A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

Claims

1. A semiconductor structure comprising:

a semiconductor-on-insulator (SOI) substrate including a handle substrate, at least one buried insulator portion abutting said handle substrate, and at least one top semiconductor portion abutting said at least one buried insulator portion;

a trench extending from a top surface of said at least one top semiconductor portion through said at least one buried insulator portion and into the handle substrate; and

a stack of an insulator stressor plug and a silicon oxide plug located in said trench, wherein said insulator stressor plug comprises a nitride and abuts a bottom surface of said trench that is present in the handle substrate and said silicon oxide plug is substantially coplanar with said top surface of said at least one top semiconductor portion, the insulator stressor plug filling the entirety of the trench that is present between the silicon oxide plug and the bottom surface of the trench, wherein an interface between said insulator stressor plug and said silicon oxide plug is located between said top surface of said at least one top semiconductor portion and a bottom surface of said at least one top semiconductor portion, or at said bottom surface of said at least one top semiconductor portion.

2. The semiconductor structure of claim 1, wherein said nitride of the insulator stressor plug is silicon nitride and applies a tensile stress or a compressive stress to said at least one top semiconductor portion.

3. The semiconductor structure of claim 2, wherein a magnitude of said tensile stress or said compressive stress is greater than 0.2 GPa in a region in said at least one top semiconductor portion.

4. The semiconductor structure of claim 1, wherein said insulator stressor plug laterally abuts, and encloses, said at least one buried insulator portion.

5. The semiconductor structure of claim 4, wherein said insulator stressor plug laterally abuts and encloses said at least one top semiconductor portion.

6. The semiconductor structure of claim 1, wherein said at least one top semiconductor portion comprises one of silicon, germanium, a silicon germanium alloy, a silicon carbon alloy, and a silicon germanium carbon alloy.

7. The semiconductor structure of claim 1, wherein a thickness of said at least one top semiconductor portion is from about 5 nm to about 300 nm, and wherein a depth of said trench is from about 200 nm to about 8,000 nm.

8. The semiconductor structure of claim 1, wherein a magnitude of a tensile stress or a compressive stress is applied by the insulator stressor plug greater than 0.2 GPa in said handle substrate.

9. The semiconductor structure of claim 1, wherein said handle substrate comprises silicon.

10. The semiconductor structure of claim 1, wherein the buried insulator portion comprises silicon oxide or silicon nitride.

11. The semiconductor structure of claim 1, wherein the buried insulator portion has a thickness ranging from 50 nm to 400 nm.

12. The semiconductor structure of claim 1, wherein the insulator stressor plug has a thickness ranging from 25 nm to 300 nm.

13. The semiconductor structure of claim 1, wherein the silicon oxide plug has a thickness ranging from 25 nm to 300 nm.