Bulk silicon moving member with dimple

• US 8,629,516 B2
• Filed: 11/21/2012
• Issued: 01/14/2014
• Est. Priority Date: 01/13/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Shu, Chia-Pao, Chu, Chia-Hua
• Primary Examiner(s): Ghyka, Alexander
• Assistant Examiner(s): ISAAC, STANETTA D
• Application Number:
  US13/683,004
• Publication Number:
  US 20130075834A1
• Time in Patent Office: 419 Days
• Field of Search: 257/415
• US Class Current: 257/415
• CPC Class Codes: B81B 3/001 Structures having a reduced contact area, e.g. with bumps or with a textured surface
• CPC Class Codes: H01L 29/84 controllable by variation of applied mechanical force, e.g. of pressure

Abstract

A method for forming a semiconductor device includes forming a substrate, forming a moveable member of bulk silicon and forming a first dimple structure on a first surface of the moveable member, where the first surface faces the substrate.

Claims

1. A semiconductor device, comprising:

a substrate;

an insulator layer over the substrate, the insulator layer including two portions surrounding a cavity, at least one of the portions including a first signaling component; and

a bulk silicon layer over the insulator layer, the bulk silicon layer including three portions,

wherein two of the three portions of the bulk silicon layer are over the two portions of the insulator layer, wherein one of the two portions of the bulk silicon layer includes a second signaling component to engage with the first signaling component, and wherein the third portion of the bulk silicon layer is separate from the other two portions and is disposed within the cavity;

a first dimple on the third portion of the bulk silicon layer and extending into the cavity;

a second dimple on the third portion of the bulk silicon layer and extending away from the cavity; and

a first layer over the two portions of the bulk silicon layer, but not over the third portion; and

a second layer over first layer and extending over, but not in contact with, the third portion of the bulk silicon layer.

2. The semiconductor device of claim 1 wherein the first dimple and the first and second signaling components are made of polysilicon.

3. The semiconductor device of claim 1, wherein the substrate and the second layer include bulk silicon, and the insulator layer includes silicon dioxide.

4. The semiconductor device of claim 1 further comprising:

an electrode on the substrate configured to sense relative movement between the substrate and the third portion of the bulk silicon.

5. The semiconductor device of claim 4, wherein the electrode includes a polysilicon portion and an insulating portion between the polysilicon portion and the substrate.

6. The semiconductor device of claim 1 comprising a Micro-Electro-Mechanical Systems (MEMS) device, wherein the third portion of the bulk silicon layer is configured as a moveable member with an interposed polysilicon member forming an upper and lower dimple structure.

7. The semiconductor device of claim 1, wherein the first signaling component comprises a via structure in communication with a structure within a signal routing layer.

8. The semiconductor device of claim 1, wherein the first signaling component comprises a via structure in communication with a first signal routing layer and a second signal routing layer.

9. A semiconductor device comprising:

a Micro-Electro-Mechanical Systems (MEMS) device built on a substrate, the MEMS device including;

an insulator layer disposed on the substrate and defining a cavity;

a first signal routing layer formed within the insulator layer, the first signal routing layer comprising polysilicon;

a bulk silicon layer disposed on the insulator layer and including a moveable member within the cavity, the moveable member including a polysilicon dimple within the cavity; and

an upper member constraining movement of the moveable member between the substrate and the upper member.

10. The semiconductor device of claim 9, wherein the dimple is part of a polysilicon member interposed in the moveable member.

11. The semiconductor device of claim 9, wherein the bulk silicon layer further comprises a polysilicon via in communication with the first signal routing layer.

12. The semiconductor device of claim 9, further comprising a second signal routing layer in the insulator layer.

13. A semiconductor device, comprising:

a substrate;

an insulator layer over the substrate, the insulator layer including two portions surrounding a cavity, at least one of the portions including a first signaling component; and

a bulk silicon layer over the insulator layer, the bulk silicon layer including three portions,

wherein two of the three portions of the bulk silicon layer are over the two portions of the insulator layer, wherein one of the two portions of the bulk silicon layer includes a second signaling component to engage with the first signaling component, and wherein the third portion of the bulk silicon layer is separate from the other two portions and is disposed within the cavity;

wherein the semiconductor device comprises a Micro-Electro-Mechanical Systems (MEMS) device, wherein the third portion of the bulk silicon layer is configured as a moveable member with an interposed polysilicon member forming an upper and lower dimple structure.

14. The semiconductor device of claim 13, wherein the substrate and the second layer include bulk silicon, and the insulator layer includes silicon dioxide.

15. The semiconductor device of claim 13 further comprising:

an electrode on the substrate configured to sense relative movement between the substrate and the third portion of the bulk silicon.

16. The semiconductor device of claim 15, wherein the electrode includes a polysilicon portion and an insulating portion between the polysilicon portion and the substrate.

17. The semiconductor device of claim 13, wherein the first signaling component comprises a via structure in communication with a structure within a signal routing layer.

18. The semiconductor device of claim 13, wherein the first signaling component comprises a via structure in communication with a first signal routing layer and a second signal routing layer.