Thin wafer protection device

• US 8,629,565 B2
• Filed: 03/13/2012
• Issued: 01/14/2014
• Est. Priority Date: 03/27/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Ku-Feng, Wu, Weng-Jin, Chiou, Wen-Chih, Wang, Tsung-Ding
• Primary Examiner(s): CHU, CHRIS C
• Application Number:
  US13/419,078
• Publication Number:
  US 20120168962A1
• Time in Patent Office: 672 Days
• Field of Search: 257/E21.502, 257/E23.067, 257/E23.117, 257/E23.116, 257/E25.013, 257/685, 257/686, 257/723, 257/737, 257/774, 257/78, 257/777, 257/8, 438106-110, 438/112, 438/114, 438124-127, 361/760
• US Class Current: 257/777
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/80006 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/80894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/80895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/95001 : involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1421 : RF devices
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A thin wafer protection device includes a wafer having a plurality of semiconductor chips. The wafer has a first side and an opposite second side. A plurality of dies is over the first side of the wafer, and at least one of the plurality of dies is bonded to at least one of the plurality of semiconductor chips. A wafer carrier is over the second side of the wafer. An encapsulating layer is over the first side of the wafer and the plurality of dies, and the encapsulating layer has a planar top surface. An adhesive tape is over the planar top surface of the encapsulating layer.

Claims

1. A thin wafer protection device, comprising:

a wafer having a plurality of semiconductor chips, the wafer having a first side and an opposite second side;

a plurality of dies over the first side of the wafer, wherein at least one of the plurality of dies is bonded to at least one of the plurality of semiconductor chips;

a wafer carrier over the second side of the wafer;

an encapsulating layer over the first side of the wafer and the plurality of dies, wherein the encapsulating layer has a planar top surface; and

an adhesive tape over the planar top surface.

2. The thin wafer protection device of claim 1, further comprising at least one redistribution layer between the plurality of dies and the plurality of semiconductor chips.

3. The thin wafer protection device of claim 1, wherein the plurality of chips comprise radio frequency chips or logic chips.

4. The thin wafer protection device of claim 1, wherein the plurality of dies comprise memory chips, radio frequency chips or logic chips.

5. The thin wafer protection device of claim 1, wherein at least one of the plurality of dies is bonded to more than one of the plurality of semiconductor chips.

6. The thin wafer protection device of claim 1, wherein the encapsulating layer comprises polyethylene glycol, a wax, a polymer, a polymer-based material, or a combination thereof.

7. The thin wafer protection device of claim 1, wherein the encapsulating layer comprise a molecular weight of 1500 and a melting temperature greater than 45°

C.

8. The thin wafer protection device of claim 1, wherein the adhesive tape comprises dicing tape or ultraviolet tape.

9. The thin wafer protection device of claim 1, further comprising through silicon vias (TSVs) arranged to electrically connect the wafer to the plurality of dies.

10. The thin wafer protection device of claim 1, further comprising a bonding structure between the at least one of the plurality of dies and the at least one of the plurality of semiconductor chips, wherein the bonding structure comprises a solder bump or a copper post.

11. The thin wafer protection device of claim 1, wherein the adhesive tape comprises dicing tape or ultraviolet tape.

12. A thin wafer protection device, comprising:

a wafer having a plurality of semiconductor chips, the wafer having a first side and an opposite second side;

a plurality of dies over the first side of the wafer, wherein at least one of the plurality of dies is bonded to at least one of the plurality of semiconductor chips;

an adhesive tape over the second side of the wafer; and

an encapsulating layer over the first side of the wafer and the plurality of dies, wherein the encapsulating layer has a planar top surface.

13. The thin wafer protection device of claim 12, further comprising at least one redistribution layer between the plurality of dies and the plurality of semiconductor chips.

14. The thin wafer protection device of claim 12, wherein the plurality of chips comprise radio frequency chips or logic chips.

15. The thin wafer protection device of claim 12, wherein the plurality of dies comprise memory chips, radio frequency chips or logic chips.

16. The thin wafer protection device of claim 12, wherein at least one of the plurality of dies is bonded to more than one of the plurality of semiconductor chips.

17. The thin wafer protection device of claim 12, wherein the encapsulating layer comprises polyethylene glycol, a wax, a polymer, a polymer-based material, or a combination thereof.

18. The thin wafer protection device of claim 12, wherein the encapsulating layer comprise a molecular weight of 1500 and a melting temperature greater than 45°

C.

19. A thin wafer protection device, comprising:

a wafer having a plurality of semiconductor chips, the wafer having a first side and an opposite second side;

a plurality of dies over the first side of the wafer, wherein at least one of the plurality of dies is bonded to at least one of the plurality of semiconductor chips; and

an adhesive tape over the second side of the wafer.

20. The thin wafer protection device of claim 19, further comprising through silicon vias (TSVs) arranged to electrically connect the wafer to the plurality of dies.