Semiconductor memory device

• US 8,630,110 B2
• Filed: 04/30/2012
• Issued: 01/14/2014
• Est. Priority Date: 05/06/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Endo, Masami
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US13/459,566
• Publication Number:
  US 20120281456A1
• Time in Patent Office: 624 Days
• Field of Search: 365/149, 365/233.1
• US Class Current: 365/149
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G11C 14/0054 in which the volatile element is a SRAM cell
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

The semiconductor memory device includes: a memory circuit including a transistor including an oxide semiconductor in a semiconductor layer; a capacitor for storing electric charge for reading data retained in the memory circuit; a charge storage circuit for controlling storage of electric charge in the capacitor; a data detection circuit for controlling data reading; a timing control circuit for generating a first signal controlling storage of electric charge in the capacitor (storage is conducted with the charge storage circuit, and the first signal is generated with a second signal at a supply voltage and a third signal delayed from the second signal at the supply voltage in a period immediately after the supply of the supply voltage); an inverter circuit for outputting a potential obtained by inverting a potential of one electrode of the capacitor.

Claims

1. A semiconductor memory device comprising:

a memory circuit, the memory circuit comprising;

a first transistor, the first transistor comprising;

a first terminal electrically connected to a data input line;

a second terminal;

a gate electrically connected to a clock signal line; and

a semiconductor layer comprising an oxide semiconductor,

a first capacitor comprising an electrode electrically connected to the second terminal of the first transistor; and

a second transistor comprising a gate electrically connected to the second terminal of the first transistor and to the electrode of the first capacitor,

a second capacitor configured to store electric charge for reading data retained in the memory circuit;

a charge storage circuit electrically connected to a supply potential line, the charge storage circuit controlling storage of electric charge in the second capacitor;

a data detection circuit configured to control conduction or non-conduction between an electrode of the second capacitor and a first terminal of the second transistor,

a timing control circuit configured to cause the charge storage circuit and the data detection circuit to be alternately brought into a conductive state in accordance with toggling of a clock signal in a first period in which the clock signal is supplied to the clock signal line, and to generate a first signal that controls storage of electric charge in the second capacitor, the storage being conducted with the charge storage circuit, the first signal being generated with a second signal at a supply voltage and a third signal delayed from the second signal at the supply voltage in a second period immediately after the supply voltage is supplied to the supply potential line; and

an inverter circuit configured to output a potential obtained by inverting a potential of the electrode of the second capacitor.

2. The semiconductor memory device according to claim 1, wherein the second transistor comprises silicon in a semiconductor layer.

3. The semiconductor memory device according to claim 2, wherein the first transistor and the second transistor are stacked each other.

4. The semiconductor memory device according to claim 1, wherein the data detection circuit is a circuit configured to convert a potential of the electrode of the second capacitor into an inverted data signal having inverted data in accordance with discharge and non-discharge of the electric charge stored in the second capacitor, the discharge and non-discharge being determined by a conducting state of the second transistor.

5. The semiconductor memory device according to claim 1, wherein a circuit for delaying the signal at the supply potential comprises a delay circuit and a buffer circuit.

6. The semiconductor memory device according to claim 1, wherein the timing control circuit comprises a non-conjunction circuit receiving a signal at the supply potential and a signal delayed from the signal at the supply potential, and a disjunction circuit receiving an output signal of the non-conjunction circuit and the clock signal.

7. A semiconductor memory device comprising:

a memory circuit, the memory circuit comprising;

a first transistor, the first transistor comprising;

a first terminal electrically connected to a data input line;

a second terminal;

a gate electrically connected to a clock signal line; and

a semiconductor layer comprising an oxide semiconductor,

a first capacitor comprising an electrode electrically connected to the second terminal of the first transistor; and

a second transistor comprising a gate electrically connected to the second terminal of the first transistor and to the electrode of the first capacitor,

a second capacitor configured to store electric charge for reading data retained in the memory circuit;

a charge storage circuit comprising a third transistor comprising a first terminal electrically connected to a supply potential line and a second terminal electrically connected to an electrode of the second capacitor;

a data detection circuit comprising a fourth transistor comprising a first terminal electrically connected to the electrode of the second capacitor and a second terminal electrically connected to a first terminal of the second transistor;

a timing control circuit configured to cause the third transistor and the fourth transistor to be alternately brought into a conductive state in accordance with toggling of the clock signal in a first period in which the clock signal is supplied to the clock signal line, and to generate a first signal for bringing the third transistor into a conductive state, the first signal being generated with a second signal at a supply voltage and a third signal delayed from the second signal at the supply voltage in a second period immediately after the supply voltage is supplied to the supply potential line; and

an inverter circuit configured to output a potential obtained by inverting a potential of the electrode of the second capacitor.

8. The semiconductor memory device according to claim 7, wherein the second transistor comprises silicon in a semiconductor layer.

9. The semiconductor memory device according to claim 8, wherein the first transistor and the second transistor are stacked each other.

10. The semiconductor memory device according to claim 7, wherein the data detection circuit is a circuit configured to convert a potential of the electrode of the second capacitor into an inverted data signal having inverted data in accordance with discharge and non-discharge of the electric charge stored in the second capacitor, the discharge and non-discharge being determined by a conducting state of the second transistor.

11. The semiconductor memory device according to claim 7, wherein a circuit for delaying the signal at the supply potential comprises a delay circuit and a buffer circuit.

12. The semiconductor memory device according to claim 7, wherein the timing control circuit comprises a non-conjunction circuit receiving a signal at the supply potential and a signal delayed from the signal at the supply potential, and a disjunction circuit receiving an output signal of the non-conjunction circuit and the clock signal.

13. A semiconductor memory device comprising:

a memory circuit, the memory circuit comprising;

a first transistor, the first transistor comprising;

a first terminal electrically connected to a data input line;

a second terminal;

a gate electrically connected to a clock signal line; and

a semiconductor layer comprising an oxide semiconductor,

a first capacitor comprising an electrode electrically connected to the second terminal of the first transistor; and

a second transistor comprising a gate electrically connected to the second terminal of the first transistor;

a second capacitor;

a third transistor comprising a first terminal electrically connected to a supply potential line and a second terminal electrically connected to an electrode of the second capacitor;

a fourth transistor comprising a first terminal electrically connected to the electrode of the second capacitor and a second terminal electrically connected to a first terminal of the second transistor;

a timing control circuit electrically connected to the gate of the first transistor, a gate of the third transistor, a gate of the fourth transistor, the supply potential line, and a delay supply potential line; and

an inverter circuit electrically connected to the electrode of the second capacitor.

14. The semiconductor memory device according to claim 13,

wherein the clock signal line supplies a clock signal,

wherein the supply potential line supplies a supply voltage,

wherein the delay supply potential line supplies a delay supply potential signal, and

wherein the timing control circuit is configured to control the third transistor and the fourth transistor in accordance with the clock signal, the supply voltage, and the delay supply potential signal.

15. The semiconductor memory device according to claim 13, wherein the second transistor comprises silicon in a semiconductor layer.

16. The semiconductor memory device according to claim 14, wherein the first transistor and the second transistor are stacked each other.

17. The semiconductor memory device according to claim 13, further comprising a circuit comprising a delay circuit and a buffer circuit,

wherein the circuit is electrically connected to the delay supply potential line.