Memory devices and methods for high random transaction rate

• US 8,630,111 B2
• Filed: 04/09/2013
• Issued: 01/14/2014
• Est. Priority Date: 01/13/2011
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Barbara, Bruce, Marino, John, Maheshwari, Dinesh
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US13/859,669
• Publication Number:
  US 20130223165A1
• Time in Patent Office: 280 Days
• Field of Search: 365/154, 365/156, 365/230.05, 365/230.01, 365/230.03, 365/230.06, 365/233.1, 365/233.11
• US Class Current: 365/154
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory device can include a random access memory array configured to store data values; a plurality of bi-directional ports, configured to transfer data values into and out of the memory device on rising and falling transitions of at least one access clock signal; and at least one address bus configured to receive at least a portion of address values to random access locations on rising and falling transitions a timing clock signal having the same frequency as the access clock signal.

Claims

1. A memory device, comprising:

a random access memory array configured to store data values;

a plurality of bi-directional ports, configured to transfer data values into and out of the memory device on rising and falling transitions of at least one clock signal; and

at least one address bus configured to receive at least a portion of address values to random access locations on rising and falling transitions of another clock signal having the same frequency as the one clock signal.

2. The memory device of claim 1, wherein:

the at least one clock signal includes a write clock signal; and

each bi-directional port is configured to receive write data in synchronism with rising and falling edges of the write clock signal;

wherein

the write clock signal has the same frequency as the other clock signal.

3. The memory device of claim 1, wherein:

the at least one clock signal includes a read clock signal; and

each bi-directional port is configured to output read data in synchronism with rising and falling edges of the read clock signal;

wherein

the read clock signal has the same frequency as the other clock signal.

4. The memory device of claim 3, wherein:

a timing control circuit configurable to phase shift the read clock signal with respect to the other clock signal.

5. The memory device of claim 1, further including:

write circuits configured to write data to the random access memory array in response to write commands on either the rising or falling edges of the one clock signal.

6. The memory device of claim 5, further including:

the random access memory array includes a plurality of different banks; and

the write circuits are further configured to prevent a write to one bank in response to a write command if the same bank was accessed by a previous read command or previous write command received in the same cycle of the one clock signal as the write command.

7. The memory device of claim 1, further including:

read circuits configured to read data from the random access memory array on either the rising or falling edges of the one clock signal.

8. The memory device of claim 5, further including:

the random access memory array includes a plurality of different banks; and

the read circuits are further configured to prevent a read to one bank in response to a read command if the same bank was accessed by a previous read command or previous write command received in the same clock cycle of the one clock signal as the read command.

9. A memory device, comprising:

a plurality of bi-directional data ports, each comprising a set of data input/outputs (I/Os) configured to receive write data or output read data;

at least one address bus configured to receive at least a portion of a read or write address at different times in the same cycle of a periodic timing signal, each read or write address of the same cycle corresponding to a different port; and

a random access memory array coupled to each port and to the address bus and configured to store write data received on a port in response to a write transfer and to provide read data to a port in response to a read transfer.

10. The memory device of claim 9, further including:

a command input configured to receive command inputs at different times in the same clock cycle of the periodic timing signal, each command input of the same clock cycle corresponding to a different port.

11. The memory device of claim 9, wherein:

each port is configured to transfer data values at different times in the same cycle of a clock signal.

12. The memory device of claim 9, wherein:

each port comprises a double data rate (DDR) port and is configured to transfer data values in synchronism with rising and falling edges of at least one clock signal.

13. The memory device of claim 9, wherein:

each port is configured to receive write data in synchronism with a periodic write clock signal and output read data in synchronism with a periodic read clock signal.

14. The memory device of claim 9, further including:

a plurality of address registers, each address register configured to store an address value received on the address bus at a different time in the same cycle of the periodic timing signal.

15. A method, comprising:

in response to at least a first command received in a first portion of a clock cycle, transferring a first plurality of data bits between a random access memory array and a bi-directional first port; and

in response to a second command received in a second portion of the same clock cycle, selectively transferring a second plurality of data bits between the random access memory array and a bi-directional second port;

wherein

the first command and the second command can be either read or write commands.

16. The method of claim 15, further including:

receiving at least a portion of a first address with the first command; and

receiving at least a portion of a second address with the second command.

17. The method of claim 15, wherein:

transferring the first plurality of data bits includes transferring the data bits in synchronism with a rising or falling edge of a clock signal.

18. The method of claim 15, wherein:

transferring the first plurality of data bits includes

transferring write data to the random access memory array in synchronism with rising or falling edge of a write access clock, and

transferring read data from the memory device in synchronism with rising or falling edge of a read access clock.

19. The method of claim 15, further including:

selectively transferring the second plurality of data bits includes

preventing the transfer of the second plurality of data bits if accesses corresponding to the first command and second command are directed to a same bank of the random access memory array.

20. The method of claim 15, wherein:

the first command is valid on one edge of the clock cycle; and

the second command is valid on another edge of the same clock cycle.