Memory devices and methods for high random transaction rate
First Claim
Patent Images
1. A memory device, comprising:
- a random access memory array configured to store data values;
a plurality of bi-directional ports, configured to transfer data values into and out of the memory device on rising and falling transitions of at least one clock signal; and
at least one address bus configured to receive at least a portion of address values to random access locations on rising and falling transitions of another clock signal having the same frequency as the one clock signal.
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Abstract
A memory device can include a random access memory array configured to store data values; a plurality of bi-directional ports, configured to transfer data values into and out of the memory device on rising and falling transitions of at least one access clock signal; and at least one address bus configured to receive at least a portion of address values to random access locations on rising and falling transitions a timing clock signal having the same frequency as the access clock signal.
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Citations
20 Claims
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1. A memory device, comprising:
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a random access memory array configured to store data values; a plurality of bi-directional ports, configured to transfer data values into and out of the memory device on rising and falling transitions of at least one clock signal; and at least one address bus configured to receive at least a portion of address values to random access locations on rising and falling transitions of another clock signal having the same frequency as the one clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory device, comprising:
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a plurality of bi-directional data ports, each comprising a set of data input/outputs (I/Os) configured to receive write data or output read data; at least one address bus configured to receive at least a portion of a read or write address at different times in the same cycle of a periodic timing signal, each read or write address of the same cycle corresponding to a different port; and a random access memory array coupled to each port and to the address bus and configured to store write data received on a port in response to a write transfer and to provide read data to a port in response to a read transfer. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A method, comprising:
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in response to at least a first command received in a first portion of a clock cycle, transferring a first plurality of data bits between a random access memory array and a bi-directional first port; and in response to a second command received in a second portion of the same clock cycle, selectively transferring a second plurality of data bits between the random access memory array and a bi-directional second port;
whereinthe first command and the second command can be either read or write commands. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification