Semiconductor device and method for driving the same

• US 8,630,127 B2
• Filed: 06/22/2011
• Issued: 01/14/2014
• Est. Priority Date: 06/25/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Uochi, Hideki, Kamata, Koichiro
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US13/166,029
• Publication Number:
  US 20110317500A1
• Time in Patent Office: 937 Days
• Field of Search: 365/185.01, 365/185.02, 365/185.03, 365/185.05, 365/185.06, 365/185.1, 365/185.11, 365/185.17, 365/185.21, 365/185.22, 365189011-2257
• US Class Current: 365/189.011
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0045 Read using current through the cell
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2213/53 Structure wherein the resistive material being in a transistor, e.g. gate
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on the potential of the storage gate and the potential of the control gate. Data is written by setting the potential of the control gate to allow the storage gate to be a conductor, supplying a potential of data to be stored to the storage gate, and setting the potential of the control gate to allow the storage gate to be an insulator. Data is read by supplying a potential for reading to a read signal line connected to one of a source and a drain of the transistor and detecting the change in potential of a bit line connected to the other of the source and the drain.

Claims

1. A semiconductor device comprising:

a transistor including a control gate and a storage gate;

a word line;

a data line;

a read signal line; and

a bit line,

wherein the control gate is electrically connected to the word line,

wherein the storage gate is electrically connected to the data line,

wherein one of a source and a drain of the transistor is electrically connected to the read signal line, and

wherein the other of the source and the drain of the transistor is electrically connected to the bit line.

2. The semiconductor device according to claim 1, wherein the storage gate comprises an oxide semiconductor.

3. The semiconductor device according to claim 1,

wherein the transistor includes a semiconductor layer in which a channel is formed, and

wherein the storage gate is placed between the control gate and the semiconductor layer.

4. The semiconductor device according to claim 3, wherein the storage gate is placed to overlap with the channel.

5. The semiconductor device according to claim 3, wherein the storage gate is placed to overlap with the channel with an insulating layer provided therebetween and is in contact with the insulating layer.

6. A semiconductor device comprising:

a transistor comprising;

a first gate;

a first insulating layer over the first gate;

a second gate over the first insulating layer;

a second insulating layer over the second gate;

a semiconductor layer over the second insulating layer; and

a first terminal and a second terminal over the semiconductor layer;

a first line electrically connected to the first gate;

a second line electrically connected to the second gate;

a third line electrically connected to the first terminal; and

a fourth line electrically connected to the second terminal,

wherein the second gate comprises an oxide semiconductor.

7. The semiconductor device according to claim 6, wherein the semiconductor layer comprises silicon or germanium.

8. The semiconductor device according to claim 6, wherein the semiconductor layer is an oxide semiconductor layer.

9. The semiconductor device according to claim 6, further comprising a third insulating layer over the first terminal and the second terminal,

wherein the third insulating layer is in contact with the semiconductor layer.

10. The semiconductor device according to claim 6, further comprising a third gate over the first terminal and the second terminal.