SRAM read and write assist apparatus

• US 8,630,132 B2
• Filed: 05/31/2011
• Issued: 01/14/2014
• Est. Priority Date: 05/31/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Cheng, Chiting, Chou, Chung-Cheng, Chang, Jonathan Tsung-Yung
• Primary Examiner(s): Nguyen, Tuan T.
• Application Number:
  US13/149,611
• Publication Number:
  US 20120307574A1
• Time in Patent Office: 959 Days
• Field of Search: 365/189.14, 365/189.07
• US Class Current: 365/189.14
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits

Abstract

A SRAM READ and WRITE assist apparatus comprises a bit line voltage tracking block, a READ assist timer, a READ assist unit, a WRITE assist unit a WRITE control unit. The bit line voltage tracking block detects a voltage on a tracking bit line coupled to a plurality of tracking memory cells. In response to the voltage drop on the tracking bit line, the READ assist timer generates a READ assist pulse. When the READ assist pulse has a logic high state, an activated word line is pulled down to a lower voltage. Such a lower voltage helps to improve the robustness of SRAM memory circuits so as to avoid READ and WRITE failures.

Claims

1. An apparatus comprising:

a plurality of bit line tracking memory cells, each of which corresponds to a word line of a memory bank, wherein the plurality of bit line tracking memory cells are arranged in a column and coupled to a tracking bit line;

a bit line voltage tracking block coupled to the tracking bit line;

a READ assist timer coupled to the bit line voltage tracking block, wherein the READ assist timer generates a READ assist pulse; and

a READ assist unit configured to pull a voltage of a word line down to a lower level than a normal voltage of the word line when the READ assist pulse has a logic high state.

2. The apparatus of claim 1, wherein a tracking memory cell performs a READ “

0”

operation when a corresponding word line is activated.

3. The apparatus of claim 1, wherein a plurality of tracking memory cells perform a READ “

0”

operation when a corresponding word line is activated.

4. The apparatus of claim 1, wherein the READ assist pulse is terminated when a voltage on the tracking bit line is less than a predetermined value.

5. The apparatus of claim 1, wherein the READ assist unit comprises an n-type metal oxide semiconductor (NMOS) transistor comprising:

a drain coupled to a word line of the memory bank;

a source coupled to ground; and

a gate coupled to the READ assist pulse.

6. The apparatus of claim 1, wherein the READ assist unit comprises a p-type metal oxide semiconductor (PMOS) transistor comprising:

a source coupled to a word line of the memory bank;

a drain coupled to ground; and

a gate coupled to the READ assist pulse via an inverter.

7. The apparatus of claim 1, further comprising:

a WRITE assist unit configured to generate a WRITE assist pulse in response to the READ assist pulse, wherein the WRITE assist unit generates a WRITE assist pulse having a width inversely proportional to an operating voltage of the memory bank; and

a WRITE control unit configured to pull an operating voltage of the memory bank down to a lower level than a normal operating voltage of the memory bank when the WRITE assist pulse has a logic high state.

8. The apparatus of claim 1, further comprising a word line driver configured to activate a word line by decoding an address.

9. A system comprising:

a plurality of tracking memory cells arranged in a column;

a memory bank having a plurality of memory cells arranged in a plurality of rows, each of which is coupled to a word line; and

a READ and WRITE assist apparatus comprising;

a bit line voltage tracking block configured to detect a voltage on a tracking bit line coupled to the plurality of tracking memory cells;

a READ assist timer coupled to the bit line voltage tracking block, wherein the READ assist timer generates a READ assist pulse;

a READ assist unit configured to pull a voltage of a word line down to a lower level than a normal voltage of the word line when the READ assist pulse has a logic high state;

a WRITE assist unit configured to generate a WRITE assist pulse in response to the READ assist pulse; and

a WRITE control unit configured to pull an operating voltage of the memory bank down to a lower level than a normal operating voltage of the memory bank when the WRITE assist pulse has a logic high state.

10. The system of claim 9, further comprising a word line driver comprising:

an inverter having an input coupled to an NAND gate and an output coupled to a word line of the memory bank, wherein the word line is selected when the NAND gate receives a decoded address.

11. The system of claim 9, wherein the WRITE assist unit is configured such that:

a WRITE assist pulse starts from a leading edge of a READ assist pulse when the memory bank operates in a high speed mode; and

a WRITE assist pulse starts from a trailing edge of the READ assist pulse when the memory bank operates in a low power mode.

12. The system of claim 11, wherein the WRITE assist pulse is inversely proportional to an operating voltage of the memory bank.

13. The system of claim 9, wherein the tracking memory cells perform a READ “

0”

operation when a corresponding word line is selected.

14. The system of claim 9, wherein a word line voltage is pulled down to a lower voltage when the READ assist pulse has a logic high state.

15. A method comprising:

performing a READ “

0”

operation at a plurality of tracking memory cells coupled to a tracking bit line;

detecting a voltage on the tracking bit line;

generating a READ assist pulse; and

terminating the READ assist pulse when the voltage on the tracking bit line drops below a predetermined value.

16. The method of claim 15, further comprising:

pulling down a voltage on an activated word line when the READ assist pulse has a logic high state.

17. The method of claim 15, further comprising:

generating a WRITE assist pulse, wherein the WRITE assist pulse starts at a leading edge of the READ assist pulse when a memory bank operates in a high speed mode; and

reducing an operating voltage of the memory bank to a lower level than a normal operating voltage of the memory bank when the WRITE assist pulse has a logic high state.

18. The method of claim 15, further comprising:

generating a WRITE assist pulse, wherein the WRITE assist pulse starts at a trailing edge of the READ assist pulse when a memory bank operates in a low power mode; and

reducing an operating voltage of the memory bank to a lower level than a normal operating voltage of the memory bank when the WRITE assist pulse has a logic high state.

19. The method of claim 18, further comprising:

generating a width of the WRITE assist pulse, wherein the width of the WRITE assist pulse is inversely proportional to the operating voltage of a memory bank.

20. The method of claim 15, further comprising:

receiving an address;

decoding the address; and

activating a word line by a word line driver based upon a decoded address.