Memory system with calibrated data communication
First Claim
1. An integrated circuit device comprising:
- a transmitter circuit operable to transmit a timing signal over a first wire to a dynamic random access memory (DRAM), where the DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value; and
a receiver circuit operable to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire,where the transmitter circuit;
in a first mode, repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and
in a second mode, transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values, in connection with a write operation to the DRAM.
1 Assignment
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Accused Products
Abstract
An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.
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Citations
12 Claims
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1. An integrated circuit device comprising:
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a transmitter circuit operable to transmit a timing signal over a first wire to a dynamic random access memory (DRAM), where the DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value; and a receiver circuit operable to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire, where the transmitter circuit; in a first mode, repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values, in connection with a write operation to the DRAM. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification