Signal generator based device security

• US 8,630,410 B2
• Filed: 01/24/2007
• Issued: 01/14/2014
• Est. Priority Date: 01/24/2006
• Status: Expired due to Fees

• Current Assignee: Verayo, Inc.
• Original Assignee: Verayo, Inc.
• Inventors: Devadas, Srinivas, Suh, Gookwon Edward
• Primary Examiner(s): Patel, Ashok
• Assistant Examiner(s): Mangialaschi, Tracy
• Application Number:
  US11/626,639
• Publication Number:
  US 20070250938A1
• Time in Patent Office: 2,547 Days
• Field of Search: 713/181, 713/189, 340/505, 380/44, 726/34
• US Class Current: 380/44
• CPC Class Codes: G06F 21/31 User authentication
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 2221/2129 Authenticate client device independently of the user
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/0866 involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics

Abstract

Subsets of multiple signal generator circuits embodied in a device are selected, and then a volatile value for the device is generated from the selected subsets. The volatile value may be used for authentication of the device and/or for cryptographic procedures performed on the device. The signal generator circuits may each comprise an oscillator circuit, and the selection of the subsets may be according to a comparison of the outputs of the subsets of circuits, for example, according to a comparison of output oscillation frequencies.

Claims

1. A method comprising:

repeatedly regenerating a cryptographic key in an integrated circuit;

wherein regenerating the key includes;

for each of a series of portions of a volatile value,

selecting a configuration of a plurality of fixed oscillator circuits embodied in the integrated circuit, the configuration including a first plurality of oscillator circuits and a second plurality of oscillator circuits, the oscillation frequency of each oscillator circuit depending on fabrication characteristics of the semiconductor device,

generating a plurality of numerical values, including generating a first numerical value dependent on the oscillation frequency of each of the oscillator circuits of the first plurality of oscillator circuits, and generating a second numerical value dependent on the oscillation frequency of each of the oscillator circuits of the second plurality of oscillator circuits, and

forming the portion of the volatile value using the first numerical value and the second numerical value; and

generating the cryptographic key using the volatile value.

2. The method of claim 1 wherein generating the cryptographic key using the volatile value includes error correcting the volatile value.

3. The method of claim 1 wherein generating the plurality of numerical values includes applying a positive contribution to at least one of the numerical values according to the oscillation frequency of each of a plurality of the oscillator circuits and applying a negative contribution to at least one of the numerical values according to the oscillation frequency of each of a plurality of the oscillator circuits.

4. The method of claim 3 wherein generating the first numerical value includes applying a positive contribution according to the oscillation frequency of at least one of the oscillator circuits and applying a negative contribution according to the oscillation frequency of at least another of the oscillator circuits.

5. The method of claim 4 wherein at least one of generating the first numerical value and using the first numerical value in forming the volatile value includes applying a non-linear operation to a value dependent on the oscillation frequencies of a plurality of the oscillator circuits.

6. The method of claim 1 further comprising accepting a seed value, and determining the configuration for each of the plurality of portions of the volatile value from the seed value.

7. The method of claim 6 wherein determining the configuration for each of the plurality of portions includes applying a Linear Feedback Shift Register (LFSR) initialized according to the seed value.