Processor and method of determining a normalization count

• US 8,631,056 B2
• Filed: 01/09/2008
• Issued: 01/14/2014
• Est. Priority Date: 01/09/2008
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Krithivasan, Shankar, Plondke, Erich James, Codrescu, Lucian, Zeng, Mao
• Primary Examiner(s): Yaary, Michael D
• Application Number:
  US11/971,230
• Publication Number:
  US 20090177724A1
• Time in Patent Office: 2,197 Days
• Field of Search: None
• US Class Current: 708/205
• CPC Class Codes: G06F 7/49936 Normalisation mentioned as feature only
• CPC Class Codes: G06F 7/74 Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders with shifting G06F5/01

Abstract

In a particular embodiment, a method is disclosed that includes receiving an operand to be normalized at a normalization logic circuit, where the operand includes a plurality of bits. The method further includes generating a zero output when a value of the operand is equal to zero and, when the value is not equal to zero, generating an output value representing a number that is one less than a count of leading bits of the operand.

Claims

1. A method comprising:

receiving an operand at a normalization logic circuit, the operand including a plurality of bits; and

generating a first shift amount having a value representing a number that is one less than a count of leading bits of the operand when a value of the operand is not equal to zero, wherein generating the first shift amount comprises;

extracting a most significant bit from the plurality of bits;

shifting remaining bits of the plurality of bits left by one bit to produce a plurality of shifted bits;

inserting a zero value in a least significant bit of the plurality of shifted bits;

counting a leading number of zeros in the plurality of shifted bits to produce a gross shift amount; and

masking a most significant bit of the gross shift amount.

2. The method of claim 1, further comprising receiving a normalization instruction that is executable by an execution unit of a processor.

3. The method of claim 2, wherein the operand is received after receiving the normalization instruction.

4. The method of claim 1, further comprising:

generating a second shift amount having a zero value when the value of the operand is equal to zero.

5. The method of claim 1, wherein masking the most significant bit of the gross shift amount comprises providing the most significant bit to an input of a logical AND gate that includes a second input coupled to a logical zero value.

6. The method of claim 4, further comprising providing the first shift amount or the second shift amount to an output of the normalization logic circuit.

7. The method of claim 4, wherein generating the second shift amount comprises:

determining that the received operand has a value of zero; and

generating a logic signal to provide the second shift amount to the output of the normalization circuit.

8. A processor comprising:

an instruction execution unit configured to execute a normalization instruction, the instruction execution unit comprising;

an input adapted to receive an operand comprising a plurality of bits;

a most significant bit extraction circuit coupled to the input and adapted to extract a most significant bit from the plurality of bits;

a shifter circuit coupled to the input, the shifter circuit adapted to;

shift remaining bits of the plurality of bits left by one bit to produce a plurality of shifted bits; and

insert a zero value in a least significant bit of the plurality of shifted bits;

a leading bit counting circuit adapted to count a leading number of zeros in the plurality of shifted bits to produce a gross shift amount; and

a mask circuit adapted to mask a most significant bit of the gross shift amount.

9. The processor of claim 8, wherein the mask circuit includes a logical AND gate.

10. The processor of claim 8, wherein the leading bit counting circuit comprises a leading zero counting circuit coupled to outputs of a plurality of exclusive OR gates, and wherein each exclusive OR gate of the plurality of exclusive OR gates is adapted to receive the most significant bit and a particular bit of the plurality of shifted bits.

11. The processor of claim 8, wherein the gross shift amount corresponds to a count representing a number of leading bits of the plurality of bits minus one.

12. The processor of claim 8, further comprising a control circuit configured to determine when the operand has a value of zero.

13. The processor of claim 8, wherein the shifter circuit comprises a bi-directional shifter circuit.

14. A non-transitory computer readable medium storing a normalization instruction that, when executed by an execution unit of a processor, causes the execution unit to:

receive an operand including a plurality of bits;

extract a most significant bit from the plurality of bits;

shift remaining bits of the plurality of bits left by one bit to produce a plurality of shifted bits;

insert a zero value in a least significant bit of the plurality of shifted bits;

count a leading number of zeros in the plurality of shifted bits to produce a gross shift amount; and

mask a most significant bit of the gross shift amount.

15. The non-transitory computer readable medium of claim 14, wherein the normalization instruction is executed in a single instruction cycle of the processor.

16. The non-transitory computer readable medium of claim 14, wherein the execution unit comprises normalization logic circuitry adapted to execute the normalization instruction.

17. The non-transitory computer readable medium of claim 14, wherein a value of the operand is not equal to zero.

18. A method comprising:

receiving an operand including a plurality of bits at a normalization logic circuit;

shifting, at a shifter circuit that is coupled to the normalization logic circuit, the plurality of bits left by one bit to generate a shifted plurality of bits;

inserting, at the shifter circuit, a zero value at a least significant bit of the shifted plurality of bits;

counting, at a leading bit counting circuit that is coupled to the normalization logic circuit, a leading number of bits in the shifted plurality of bits; and

outputting, from the normalization logic circuit, a count representing the leading number of bits minus one when the received plurality of bits has a non-zero value.

19. The method of claim 18, wherein counting the leading number of bits comprises:

extracting the most significant bit of the received plurality of bits;

complementing the shifted plurality of bits to produce a complemented plurality of bits when a most significant bit of the received plurality of bits has a one value; and

counting a leading number of zeros in the complemented plurality of bits.

20. The method of claim 18, wherein counting the leading number of bits comprises counting a leading number of zeros in the shifted plurality of bits.

21. The method of claim 18, further comprising providing a zero value at an output when the received operand represents a zero value.

22. A processor comprising:

means for receiving an operand including a plurality of bits; and

means for generating an output value representing a number that is one less than a count of leading bits of the operand when a value of the operand is not equal to zero, wherein the means for generating comprises;

means for extracting a most significant bit from the plurality of bits;

means for shifting remaining bits of the operand left by one bit to produce a plurality of shifted bits;

means for inserting a zero value in a least significant bit of the plurality of shifted bits;

means for counting a leading number of zeros in the plurality of shifted bits to produce a shift amount; and

means for masking a most significant bit of the shift amount.

23. The processor of claim 22, further comprising means for generating a zero output when the value of the operand is equal to zero.

24. The processor of claim 23, wherein the means for generating the zero output comprises:

means for determining a value of the received operand; and

means for generating a logic signal to provide a zero value to an output of an execution unit when the value of the operand is equal to zero.

25. The processor of claim 22, further comprising means for receiving a normalization instruction that is executable by an execution unit in a single execution cycle.

26. A non-transitory computer readable medium storing processor executable instructions that, when executed by an execution unit of a processor, causes the execution unit to:

receive an operand at a normalization logic circuit, the operand including a plurality of bits; and

generate, at a leading zeros counting circuit that is coupled to the normalization logic circuit, a first shift amount having a value representing a number that is one less than a count of leading bits of the operand when a value of the operand is not equal to zero, wherein generating the first shift amount comprises;

extracting a most significant bit from the plurality of bits;

shifting remaining bits of the plurality of bits left by one bit to produce a plurality of shifted bits;

inserting a zero value in a least significant bit of the plurality of shifted bits;

counting a leading number of zeros in the plurality of shifted bits to produce a gross shift amount; and

masking a most significant bit of the gross shift amount.

27. The non-transitory computer readable medium of claim 26, further comprising processor executable instructions that, when executed by the execution unit, cause the execution unit to generate a second shift amount having a zero value when the value of the operand is equal to zero.