Emulation of abstracted DIMMS using abstracted DRAMS
First Claim
1. A sub-system comprising:
- a memory controller configured to be connected to both a first Dual In-line Memory Module (DIMM) and a second DIMM, wherein the memory controller is configured to present a first set of chip select signals to the first DIMM and a distinct second set of chip select signals to the second DIMM; and
a physical DIMM comprising an intelligent buffer and a collection of DRAM behind the intelligent buffer;
wherein the intelligent buffer is configured tocommunicate with the memory controller,operate a first subset of the collection of DRAM as a first abstracted DIMM (aDIMM) and a second subset of the collection of DRAM as a second aDIMM, andpresent to the memory controller the first aDIMM as the first DIMM and the second aDIMM as the second DIMM;
wherein the physical DIMM and the intelligent buffer are configured to receive the first set of chip select signals and the second set of chip select signals from the memory controller; and
wherein the intelligent buffer is configured to provide the first set of chip select signals to the first subset of the collection of DRAM of the first aDIMM and to provide the second set of chip select signals to the second subset of the collection of DRAM of the second aDIMM.
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Accused Products
Abstract
One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.
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Citations
20 Claims
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1. A sub-system comprising:
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a memory controller configured to be connected to both a first Dual In-line Memory Module (DIMM) and a second DIMM, wherein the memory controller is configured to present a first set of chip select signals to the first DIMM and a distinct second set of chip select signals to the second DIMM; and a physical DIMM comprising an intelligent buffer and a collection of DRAM behind the intelligent buffer; wherein the intelligent buffer is configured to communicate with the memory controller, operate a first subset of the collection of DRAM as a first abstracted DIMM (aDIMM) and a second subset of the collection of DRAM as a second aDIMM, and present to the memory controller the first aDIMM as the first DIMM and the second aDIMM as the second DIMM; wherein the physical DIMM and the intelligent buffer are configured to receive the first set of chip select signals and the second set of chip select signals from the memory controller; and wherein the intelligent buffer is configured to provide the first set of chip select signals to the first subset of the collection of DRAM of the first aDIMM and to provide the second set of chip select signals to the second subset of the collection of DRAM of the second aDIMM. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A memory module comprising:
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a physical DIMM comprising an intelligent buffer and a collection of DRAM behind the intelligent buffer; wherein the intelligent buffer is configured to communicate with a memory controller, operate a first subset of the collection of DRAM as a first abstracted DIMM (aDIMM) and a second subset of the collection of DRAM as a second aDIMM, and present to the memory controller the first aDIMM as a first DIMM and the second aDIMM as a second DIMM; wherein the physical DIMM and the intelligent buffer are configured to receive the first set of chip select signals and the second set of chip select signals from the memory controller; and wherein the intelligent buffer is configured to provide the first set of chip select signals to the first subset of the collection of DRAM of the first aDIMM and to provide the second set of chip select signals to the second subset of the collection of DRAM of the second aDIMM. - View Dependent Claims (17, 18, 19, 20)
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Specification