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Emulation of abstracted DIMMS using abstracted DRAMS

  • US 8,631,193 B2
  • Filed: 05/17/2012
  • Issued: 01/14/2014
  • Est. Priority Date: 02/21/2008
  • Status: Active Grant
First Claim
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1. A sub-system comprising:

  • a memory controller configured to be connected to both a first Dual In-line Memory Module (DIMM) and a second DIMM, wherein the memory controller is configured to present a first set of chip select signals to the first DIMM and a distinct second set of chip select signals to the second DIMM; and

    a physical DIMM comprising an intelligent buffer and a collection of DRAM behind the intelligent buffer;

    wherein the intelligent buffer is configured tocommunicate with the memory controller,operate a first subset of the collection of DRAM as a first abstracted DIMM (aDIMM) and a second subset of the collection of DRAM as a second aDIMM, andpresent to the memory controller the first aDIMM as the first DIMM and the second aDIMM as the second DIMM;

    wherein the physical DIMM and the intelligent buffer are configured to receive the first set of chip select signals and the second set of chip select signals from the memory controller; and

    wherein the intelligent buffer is configured to provide the first set of chip select signals to the first subset of the collection of DRAM of the first aDIMM and to provide the second set of chip select signals to the second subset of the collection of DRAM of the second aDIMM.

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