Adjusting the timing of signals associated with a memory system

• US 8,631,220 B2
• Filed: 09/13/2012
• Issued: 01/14/2014
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Smith, Michael John, Rosenband, Daniel L., Wang, David T., Rajan, Suresh Natarajan
• Primary Examiner(s): Elmore, Reba I
• Application Number:
  US13/615,008
• Publication Number:
  US 20130007399A1
• Time in Patent Office: 488 Days
• Field of Search: 711/5, 711/167
• US Class Current: 711/167
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency

Abstract

A system and method are provided for adjusting the timing of signals associated with a memory system. A memory controller is provided. Additionally, at least one memory module is provided. Further, at least one interface circuit is provided, the interface circuit capable of adjusting timing of signals associated with one or more of the memory controller and the at least one memory module.

Claims

1. A sub-system, comprising:

a plurality of memory devices, wherein each memory device has an actual CAS (column address strobe) latency;

a serial presence detect (SPD) device configured to provide a simulated CAS latency to a memory controller, wherein the simulated CAS latency is set to a value that causes the memory controller to view the memory devices as having a larger CAS latency than the actual CAS latency of the memory devices; and

one or more interface circuits configured to;

perform one or more additional functions including one or more of a reliability, accessibility and serviceability (RAS) function, a power management function, or a mirroring of memory function, wherein the one or more interface circuits include additional logic to perform the additional functions; and

communicate with the memory devices and a memory controller, wherein the memory devices are configured to communicate with the one or more interface circuits using a first protocol and the one or more interface circuits are configured to communicate with the memory controller using a different, second protocol, wherein the time difference between the larger simulated CAS latency and the actual CAS latency provides time in which the additional logic can perform the one or more additional functions while the sub-system is operating.

2. The sub-system of claim 1, wherein the additional logic includes one or more of refresh management logic, power management logic, delay management logic, memory mode register logic, RAS logic, protocol translation logic, or clock management logic.

3. The sub-system of claim 2, wherein the delay management logic is configured to adjust timing of signals issued to the memory devices.

4. The sub-system of claim 3, wherein the signals include address signals, control signals, or data signals.

5. The sub-system of claim 4, wherein the control signals include refresh signals for the memory devices, and wherein the delay management logic is configured to present staggered refresh signals to the memory devices to provide the power management function.

6. The sub-system of claim 3, wherein each of the memory devices has common timing specifications for receiving commands.

7. The sub-system of claim 6, wherein the memory devices are arranged in a stack, and wherein the delay management logic is configured to adjust the timing of the signals such that the common timing specifications of the memory devices are met.

8. The sub-system of claim 1, wherein the RAS function includes a hot-swap function, a memory sparing function, or a memory mirroring function.

9. The sub-system of claim 1, wherein the power management function includes a clock enable (CKE) control function or a refresh staggering function.

10. A system, comprising:

a memory controller;

a memory module comprising;

a plurality of memory devices, wherein each memory device has an actual CAS (column address strobe) latency requirement;

a serial presence detect (SPD) device configured to provide a simulated CAS latency requirement to a memory controller, wherein the simulated CAS latency requirement is set to a value that causes the memory controller to view the memory devices as having a larger CAS latency requirement than the actual CAS latency requirement of the memory devices; and

one or more interface circuits configured to;

perform one or more additional functions including one or more of a reliability, accessibility and serviceability (RAS) function, a power management function, or a mirroring of memory function, wherein the one or more interface circuits include additional logic to perform the additional functions; and

communicate with the memory devices and a memory controller, wherein the memory devices are configured to communicate with the one or more interface circuits using a first protocol and the one or more interface circuits are configured to communicate with the memory controller using a different, second protocol, and wherein the one or more interface circuits are configured to complete performing the additional one or more functions (i) prior to the larger simulated CAS latency requirement being met and (ii) while the memory module is operating.

11. The system of claim 10, wherein the additional logic includes one or more of refresh management logic, power management logic, delay management logic, protocol translation logic, memory mode register logic, RAS logic, or clock management logic.

12. The system of claim 10, wherein the delay management logic is configured to adjust timing of signals issued to the memory devices, and wherein the signals include address signals, control signals, or data signals.

13. The system of claim 12, wherein each of the memory devices has common timing specifications for receiving commands, and wherein the delay management logic is configured to adjust the timing of the signals such that the common timing specifications of the memory devices are met.

14. The system of claim 10, wherein the RAS function includes a hot-swap function, a memory sparing function, or a memory mirroring function.

15. The system of claim 10, wherein the power management function includes a clock enable (CKE) control function or a refresh staggering function.

16. A method, comprising:

communicating with a plurality of memory devices using a first protocol and with a memory controller using a different, second protocol, wherein each memory device has an actual CAS (column address strobe) latency;

providing a simulated CAS latency to the memory controller, wherein the simulated CAS latency is set to a value that causes the memory controller to view the memory devices as having a larger CAS latency than the actual CAS latency of the memory devices; and

performing, by additional logic, one or more additional functions including one or more of a reliability, accessibility and serviceability (RAS) function, a power management function, or a mirroring of memory function, wherein the time difference between the larger simulated CAS latency and the actual CAS latency provides time in which the additional logic can perform the one or more additional functions.

17. The method of claim 16, wherein the additional logic includes one or more of refresh management logic, power management logic, delay management logic, protocol translation logic, memory mode register logic, RAS logic, or clock management logic.

18. The method of claim 16, further comprising adjusting timing of signals issued to the memory devices such that common timing specifications of the memory devices are met.

19. The method of claim 16, wherein the RAS function includes a hot-swap function, a memory sparing function, or a memory mirroring function.

20. The method of claim 16, wherein the power management function includes a clock enable (CKE) control function or a refresh staggering function.