Distributed management of a shared power source to a multi-core microprocessor

• US 8,631,256 B2
• Filed: 11/17/2011
• Issued: 01/14/2014
• Est. Priority Date: 12/22/2010
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Gaskins, Darius D.
• Primary Examiner(s): Patel, Nimesh G
• Application Number:
  US13/299,225
• Publication Number:
  US 20120166832A1
• Time in Patent Office: 789 Days
• Field of Search: 713/320, 713/324, 713/300
• US Class Current: 713/300
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Microprocessors are provided with decentralized logic and associated methods for indicating power related operating states, such as desired voltages and frequency ratios, to shared microprocessor power resources such as a voltage regulator module (VRM) and phase locked loops (PLLs). Each core is configured to generate a value to indicate a desired operating state of the core. Each core is also configured to receive a corresponding value from each other core sharing the applicable resource, and to calculate a composite value compatible with the minimal needs of each core sharing the applicable resource. Each core is further configured to conditionally drive the composite value off core to the applicable resource based on whether the core is designated as a master core for purposes of controlling or coordinating the applicable resource. The composite value is supplied to the applicable shared resource without using any active logic outside the plurality of cores.

Claims

1. A microprocessor, comprising:

pins, configured for coupling the microprocessor to a voltage identifier (VID) input of a voltage regulator module (VRM) that supplies a voltage to power the microprocessor based on a value of the VID input; and

a plurality of dies, each die comprising a plurality of cores;

wherein each core is configured to generate a first VID value that indicates the desired VID of the core and to receive the first VID value from the other cores of its die and to generate a second VID value which is the largest of the first VID values of all the cores of the die;

wherein each core is configured to provide the second VID value to at least one core of each of the other dies of the microprocessor and to receive the second VID value from at least one core of each of the other dies of the microprocessor and to generate a third VID value which is the largest of all the second VID values of the microprocessor;

wherein each core is configured to provide the third VID value to the pins if the core is a master core of the microprocessor.

2. The microprocessor of claim 1, wherein each core is configured to provide a zero value to the pins if the core is not the master core of the microprocessor.

3. The microprocessor of claim 2, wherein the third VID value from the master core and the zero values from the non-master cores are wire-OR'"'"'ed together to generate the resultant VID input value to the VRM.

4. The microprocessor of claim 1, wherein each core comprises:

a fuse that indicates whether the core is the master core of the microprocessor.

5. The microprocessor of claim 4, wherein each core comprises:

a register, writable by system software to override the fuse indication.

6. The microprocessor of claim 1, further comprising:

inter-die wires configured to convey the second VID values between the dies of the microprocessor.

7. The microprocessor of claim 6, wherein the inter-die wires comprise a plurality of serial interfaces between the dies of the microprocessor.

8. The microprocessor of claim 6, further comprising:

a substrate, upon which the plurality of dies are mounted and in which the inter-die wires are disposed.

9. The microprocessor of claim 1, wherein each die comprises:

inter-core wires configured to convey the first VID values between the cores of the die.

10. The microprocessor of claim 1, wherein the VID input value is generated by the microprocessor without any active logic outside the plurality of cores.

11. A method for operating a microprocessor having a plurality of dies each comprising a plurality of cores and pins for coupling the microprocessor to a voltage identifier (VID) input of a voltage regulator module (VRM) that supplies a voltage to power the microprocessor based on a value of the VID input, the method comprising:

generating, by each core, a first VID value that indicates the desired VID of the core;

receiving, by each core, the first VID value from the other cores of the core'"'"'s die;

generating, by each core, a second VID value which is the largest of the first VID values of all the cores of the core'"'"'s die;

providing, by each core, the second VID value to at least one core of each of the other dies of the microprocessor;

receiving, by each core, the second VID value from at least one core of each of the other dies of the microprocessor;

generating, by each core, a third VID value which is the largest of all the second VID values of the microprocessor; and

providing, by each core, the third VID value to the pins, if the core is a master core of the microprocessor and otherwise providing a zero value to the pins.

12. The method of claim 11, further comprising:

wire-OR'"'"'ing together the third VID value from the master core and the zero values from the non-master cores are to generate the resultant VID input value to the VRM.

13. The method of claim 11, further comprising:

indicating, via a fuse of each core, whether the core is the master core of the microprocessor.

14. The method of claim 11, further comprising:

conveying the second VID values between the dies of the microprocessor via inter-die wires.

15. The method of claim 11, wherein the VID input value is generated by the microprocessor without any active logic outside the plurality of cores.