Method and apparatus for quick resumption of a processing system with volatile memory

• US 8,631,259 B2
• Filed: 02/11/2013
• Issued: 01/14/2014
• Est. Priority Date: 09/15/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rothman, Michael, Hinton, Glenn, Zimmer, Vincent, Kinney, Michael, Doran, Mark
• Primary Examiner(s): TRAN, VINCENT HUY
• Application Number:
  US13/764,245
• Publication Number:
  US 20130151876A1
• Time in Patent Office: 337 Days
• Field of Search: 713/1, 713/2, 713/300
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake

Abstract

When transitioning from sleep mode to active mode, a processing system loads first stage resume content and second stage resume content into a volatile memory of the processing system. The first stage resume content may contain contextual data for a first program that was in use before the processing system transitioned to sleep mode. The second stage resume content may contain contextual data for another program that was in use before the processing system transitioned to sleep mode. The processing system may provide a user interface for the first program before all of the second stage resume content has been loaded into the volatile memory. Other embodiments are described and claimed.

Claims

1. An article of manufacture comprising:

at least one non-transitory machine-readable medium; and

instructions stored in the at least one non-transitory machine-readable medium, wherein the instructions, when executed by a processing system having volatile memory, enable the processing system to perform operations comprising;

transitioning the processing system from an active state to a sleeping state; and

after transitioning the processing system from the active state to the sleeping state, performing resume operations in response to a start event, wherein the resume operations comprise;

initializing, by system firmware, a first portion of the volatile memory but not a second portion of the volatile memory;

transitioning the processing system from the sleeping state to the active state; and

initializing, by an operating system (OS), the second portion of the volatile memory.

2. An article of manufacture according to claim 1, wherein the operations further comprise:

after transition from the sleeping state to the active state has begun but before the OS has finished initializing the second portion of the volatile memory, executing at least one user mode thread.

3. An article of manufacture according to claim 1, wherein the operation of transitioning the processing system from the sleeping state to the active state is performed before the OS has finished initializing the second portion of the volatile memory.

4. An article of manufacture according to claim 1, wherein:

the operation of transitioning the processing system from the sleeping state to the active state is performed after the system firmware has initialized the first portion of the volatile memory and before the OS has finished initializing the second portion of the volatile memory.

5. An article of manufacture according to claim 1, wherein the operations further comprise:

the OS using a firmware variable to save data indicating that the OS has assumed responsibility for initializing the second portion of the volatile memory.

6. An article of manufacture according to claim 1, wherein:

the resume operations further comprise determining, by the system firmware, whether the processing system is resuming from a non-powered sleeping state; and

the system firmware initializes the first portion of the volatile memory but not the second portion of the volatile memory, in response to a determination that the processing system is resuming from the non-powered sleeping state.

7. An article of manufacture according to claim 6, wherein:

the operations further comprise determining, by the system firmware, whether responsibility for initializing any of the volatile memory has been assigned to the OS; and

the system firmware initializes the first portion of the volatile memory but not the second portion of the volatile memory in response to determinations that (a) the processing system is resuming from a non-powered sleeping state and (b) responsibility for initializing the second portion of volatile memory has been assigned to the OS.

8. An article of manufacture according to claim 7, wherein the operations further comprise:

the OS using a firmware variable to save data indicating that the OS has assumed responsibility for initializing the second portion of the volatile memory.

9. A processing system comprising:

a processor;

volatile memory responsive to the processor;

at least one non-transitory machine-readable medium responsive to the processor; and

instructions stored in the at least one non-transitory machine-readable medium, wherein the instructions, when executed by the processing system, enable the processing system to perform operations comprising;

transitioning the processing system from an active state to a sleeping state; and

after transitioning the processing system from the active state to the sleeping state, performing resume operations in response to a start event, wherein the resume operations comprise;

initializing, by system firmware, a first portion of the volatile memory but not a second portion of the volatile memory;

transitioning the processing system from the sleeping state to the active state; and

initializing, by an operating system (OS), the second portion of the volatile memory.

10. A processing system according to claim 9, wherein the operations further comprise:

after transition from the sleeping state to the active state has begun but before the OS has finished initializing the second portion of the volatile memory, executing at least one user mode thread.

11. A processing system according to claim 9, wherein the operation of transitioning the processing system from the sleeping state to the active state is performed before the OS has finished initializing the second portion of the volatile memory.

12. A processing system according to claim 9, wherein:

the operation of transitioning the processing system from the sleeping state to the active state is performed after the system firmware has initialized the first portion of the volatile memory and before the OS has finished initializing the second portion of the volatile memory.

13. A processing system according to claim 9, wherein the operations further comprise:

the OS using a firmware variable to save data indicating that the OS has assumed responsibility for initializing the second portion of the volatile memory.

14. A processing system according to claim 9, wherein:

the resume operations further comprise determining, by the system firmware, whether the processing system is resuming from a non-powered sleeping state; and

the system firmware initializes the first portion of the volatile memory but not the second portion of the volatile memory, in response to a determination that the processing system is resuming from the non-powered sleeping state.

15. A processing system according to claim 14, wherein:

the operations further comprise determining, by the system firmware, whether responsibility for initializing any of the volatile memory has been assigned to the OS; and

the system firmware initializes the first portion of the volatile memory but not the second portion of the volatile memory in response to determinations that (a) the processing system is resuming from a non-powered sleeping state and (b) responsibility for initializing the second portion of volatile memory has been assigned to the OS.

16. A processing system according to claim 15, wherein the operations further comprise:

the OS using a firmware variable to save data indicating that the OS has assumed responsibility for initializing the second portion of the volatile memory.

17. An article of manufacture comprising:

at least one non-transitory machine-readable medium; and

instructions stored in the at least one non-transitory machine-readable medium, wherein the instructions, when executed by a processing system having volatile memory, enable the processing system to perform operations comprising;

while the processing system is in an active state, executing a program on the processing system;

transitioning the processing system from the active state to a sleeping state;

after transitioning the processing system from the active state to the sleeping state, performing resume operations in response to a start event, wherein;

the resume operations comprise consecutive first and second stage loading processes;

the first stage loading process comprises;

initializing, by system firmware, a first portion of the volatile memory but not a second portion of the volatile memory; and

after initializing the first portion of the volatile memory, loading first stage resume content into the volatile memory, wherein the first stage resume content comprises data for the program; and

the second stage loading process comprises operations to be performed by an operating system (OS), wherein the second stage loading process comprises initializing, by the OS, the second portion of the volatile memory; and

after the first stage loading process has begun but before the second stage loading process has finished, using the data for the program to present a user interface.

18. An article of manufacture according to claim 17, wherein the operations further comprise:

after the first stage loading process has begun but before the second stage loading process has finished, executing at least one user mode thread.

19. A processing system comprising:

a processor;

volatile memory responsive to the processor;

at least one non-transitory machine-readable medium responsive to the processor; and

instructions stored in the at least one non-transitory machine-readable medium, wherein the instructions, when executed by the processing system, enable the processing system to perform operations comprising;

while the processing system is in an active state, executing a program on the processing system;

transitioning the processing system from the active state to a sleeping state;

after transitioning the processing system from the active state to the sleeping state, performing resume operations in response to a start event, wherein;

the resume operations comprise consecutive first and second stage loading processes;

the first stage loading process comprises;

initializing, by system firmware, a first portion of the volatile memory but not a second portion of the volatile memory; and

after initializing the first portion of the volatile memory, loading first stage resume content into the volatile memory, wherein the first stage resume content comprises data for the program; and

the second stage loading process comprises operations to be performed by an operating system (OS), wherein the second stage loading process comprises initializing, by the OS, the second portion of the volatile memory; and

after the first stage loading process has begun but before the second stage loading process has finished, using the data for the program to present a user interface.

20. A processing system according to claim 19, wherein the operations further comprise:

after the first stage loading process has begun but before the second stage loading process has finished, executing at least one user mode thread.