Scan topology discovery in target systems

• US 8,631,289 B2
• Filed: 07/23/2013
• Issued: 01/14/2014
• Est. Priority Date: 07/29/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Swoboda, Gary L.
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US13/948,373
• Publication Number:
  US 20130311841A1
• Time in Patent Office: 175 Days
• Field of Search: 714/726, 714/727, 714/729
• US Class Current: 714/726
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
• CPC Class Codes: G01R 31/318538 Topological or mechanical aspects
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G06F 11/36 Preventing errors by testing or debugging software
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

Claims

1. A process of determining a topology of individual components in a system of components, each component having a clock lead, a control lead, a data in lead, a data out lead, and a data register of a certain length coupled between the data in lead and the data out lead, the process comprising:

A. receiving on the data in lead of each component data register scan data of one or another logic level;

B. stepping the data registers of all the components a number of times greater than the length of all the data registers; and

C. storing in a topology register of a component topology data bits indicating a topology of the component based on the logic level of the data register scan data received in that component.

2. The process of claim 1 in which the storing includes storing topology data bits indicating a series scan topology in response to receiving all 0 logic levels in a component.

3. The process of claim 1 in which the storing includes storing topology data bits 01b indicating a series scan topology in response to receiving all 0 logic levels in a component.

4. The process of claim 1 in which the storing includes storing topology data bits indicating a star 2 scan topology in response to receiving all 1 logic levels in a component.

5. The process of claim 1 in which the storing includes storing topology data bits 11b indicating a star 2 scan topology in response to receiving all 1 logic levels in a component.