Silicon device on Si: C-oi and Sgoi and method of manufacture

• US 8,633,071 B2
• Filed: 10/21/2011
• Issued: 01/21/2014
• Est. Priority Date: 11/19/2003
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dokumaci, Omer H., Gluschenkov, Oleg G., Chidambarrao, Duresti
• Primary Examiner(s): MITCHELL, JAMES M
• Application Number:
  US13/278,667
• Publication Number:
  US 20120052653A1
• Time in Patent Office: 823 Days
• Field of Search: 438/223, 438/224, 438/227
• US Class Current: 438/223
• CPC Class Codes: H01L 21/8213 the substrate being a semiconductor, using SiC technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/7378 comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/8086 Thin film JFET's

Abstract

A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.

Claims

1. A method of manufacturing a semiconductor structure, comprising:

forming a substrate;

forming shallow trench isolation (STI) of high temperature stable amorphous material in the substrate;

providing at least one material over a PFET region and an nFET region;

thermally annealing the at least one material into the substrate to form a first island and a second island of mixed material, wherein the first island and the second island have a different relaxed crystal lattice with different dimensions between atoms; and

growing a Si layer on the first island in a first region, wherein the Si layer is strained.

2. The method of claim 1, further comprising relaxing the STI, which facilitates relaxation of the first island and the second island during the thermally annealing step.

3. The method of claim 1, wherein the at least one material is Si:

C or C.

4. The method of claim 1, wherein the Si layer becomes compressively strained.

5. The method of claim 1, wherein the thermal anneal step takes place at about 1200 to 1350°

C.

6. The method of claim 1, wherein the STI comprises a material that has a lower viscosity as the temperature rises.

7. The method of claim 1, wherein:

the at least one material is Ge and the Si layer becomes tensilely strained;

the STI comprises a material that has a lower viscosity as the temperature rises; and

the at least one material and the substrate are a high temperature stable amorphous material.

8. The method of claim 1, wherein the Si layer has a different lattice constant than the first island such that the Si layer will strain one of tensilely and compressively on the first island.

9. The method of claim 1, wherein:

the at least one material is Ge, C or Si;

C and the first island and the second island is comprised substantially of a mixed material of relaxed SiGe;

the Si layer is compressively strained when the mixed material is SiGe and tensilely strained when the mixed material is Si;

C; and

the Si layer has a different lattice constant than the SiGe material and the Si;

C material and the substrate is also formed from a high temperature stable amorphous material.

10. The method of claim 1, wherein the first island has a lattice constant a≧

aSi and the second island has a lattice constant a≦

aSi.

11. The method of claim 1, wherein the substrate is part of an SOI wafer.

12. The method of claim 1, wherein the forming the STI comprises patterning an underlying Si layer.

13. The method of claim 1, wherein the STI comprises oxide material.

14. A method of manufacturing a semiconductor structure, comprising:

forming a substrate;

forming shallow trench isolation (STI) of high temperature stable amorphous material in the substrate, wherein the forming the STI comprises patterning an underlying Si layer;

providing at least one material over a PFET region and an nFET region;

thermally annealing the at least one material into the substrate to form a first island and a second island of mixed material; and

growing a Si layer on the first island in a first region, wherein the Si layer is strained.

15. The method of claim 14, wherein the first island and the second island have a different relaxed crystal lattice.

16. The method of claim 14, wherein the first island has a lattice constant a≧

aSi and the second island has a lattice constant a≦

aSi.

17. The method of claim 14, wherein the substrate is part of an SOI wafer.

18. The method of claim 14, wherein the STI comprises oxide material.