Semiconductor device with high voltage transistor

• US 8,633,075 B2
• Filed: 03/12/2013
• Issued: 01/21/2014
• Est. Priority Date: 11/09/2009
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Shima, Masashi
• Primary Examiner(s): Lee, Calvin
• Assistant Examiner(s): STOWE, SCOTT C
• Application Number:
  US13/797,084
• Publication Number:
  US 20130189820A1
• Time in Patent Office: 315 Days
• Field of Search: None
• US Class Current: 438/276
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A method for manufacturing a semiconductor includes:

• • forming an isolation region defining first, second and third active regions;
  • implanting first impurity ions of a first conductivity type to form first, second and third wells;
  • implanting second impurity ions of the first conductivity type to form first and second channel regions;
  • implanting second impurity ions of a second conductivity to form a first drain region, such that a portion of the first channel region is overlapped with the first drain region;
  • forming first, second and third gate electrodes, the first gate electrode superposing a portion of the first drain region and covering one lateral end of the first channel region;
  • forming first insulating side wall spacers and a second insulating side wall spacer on a side wall of the first gate electrode; and
  • implanting fourth impurity ions of the second conductivity type to form second drain/source regions.

Claims

1. A method for manufacturing a semiconductor device comprising:

forming an active region of a first conductivity type in a semiconductor substrate;

forming a channel region of said first conductivity type in a portion of said active region;

forming a first drain region of a second conductivity type opposite to said first conductivity type, the channel region and the first drain region partially overlapping to form an overlapped portion;

forming a gate electrode covering the overlapped portion;

after said gate electrode is formed, implanting second impurity ions of said second conductivity type into said active region by using said gate electrode as a mask;

after implanting the second impurity ions, forming an insulating film covering a side wall of said gate electrode and a portion of said first drain region; and

implanting first impurity ions of said second conductivity type into said active region, by using said gate electrode and said insulating film as a mask.

2. A method for manufacturing a semiconductor device comprising:

forming an isolation region in a semiconductor substrate, the isolation region defining first, second and third active regions;

implanting first impurity ions of a first conductivity type into said first, second and third active region to form first, second and third wells, respectively;

masking said third active region and a portion of said first active region, and implanting second impurity ions of said first conductivity type into said first and second active regions to form first and second channel regions, respectively;

implanting third impurity ions of a second conductivity type opposite to said first conductivity type into said first active region to form a first drain region, in such a manner that a portion of said first channel region is overlapped with said first drain region;

forming first, second and third gate electrodes above said first, second and third active regions, respectively, said first gate electrode superposing a portion of said first drain region and covering one lateral end of said first channel region;

forming first insulating side wall spacers on side walls of said second and third gate electrodes above said second and third active regions, respectively, and forming a second insulating side wall spacer on a side wall of said first gate electrode on a source side, and forming an insulating film extending from above a drain-side region of said first gate electrode to a location above said first drain region; and

implanting fourth impurity ions of said second conductivity type into said first, second and third active regions to form second drain/source regions.

3. The method for manufacturing a semiconductor device according to claim 2, further comprising, after said first, second and third gate electrodes are formed, masking said third active region and a portion of said first active region on a drain side, and implanting fifth impurity ions of said second conductivity type to form extension regions.

4. The method for manufacturing a semiconductor device according to claim 2, further comprising, after said first, second and third gate electrodes are formed, masking said third active region, and implanting sixth impurity ions of said second conductivity type into said first active region and said second active region to form extension regions.