Method for forming interlayer connectors in a three-dimensional stacked IC device
First Claim
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1. A method, for use with an integrated circuit device including a stack of dielectric/conductive layers, for forming interlayer connectors extending from a surface of the device to the conductive layers, the method comprising:
- creating spaced apart contact openings in a contact region of the integrated circuit through a dielectric layer with dielectric layer material separating each of the contact openings, the contact openings overlying an electrical conductor for each of W conductive layers;
the contact openings creating step comprising creating a first contact opening down to a first conductive layer;
using a set of N etch masks with 2N−
1 being less than W and 2N being greater than or equal to W, the etch masks having mask regions and spaced apart open etch regions corresponding to selected contact openings;
etching, using the N etch masks, the stack of dielectric/conductive layers only through W−
1 contact openings to create extended contact openings extending to W−
1 conductive layers;
the etching step comprising etching 2n−
1 conductive layers for up to half of the contact openings for each etch mask n=1, 2 . . . N;
the etching step being carried out so that the contact openings are etched with different combinations of the open etch regions of said etch masks; and
forming interlayer connectors in the first contact opening and the extended contact openings to electrically connect to each of the conductive layers.
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Abstract
A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N−1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W−1 contact openings to create extended contact openings extending to W−1 conductive layers; 2n−1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks'"'"' open etch regions. Interlayer connectors are formed in the contact openings.
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Citations
19 Claims
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1. A method, for use with an integrated circuit device including a stack of dielectric/conductive layers, for forming interlayer connectors extending from a surface of the device to the conductive layers, the method comprising:
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creating spaced apart contact openings in a contact region of the integrated circuit through a dielectric layer with dielectric layer material separating each of the contact openings, the contact openings overlying an electrical conductor for each of W conductive layers; the contact openings creating step comprising creating a first contact opening down to a first conductive layer; using a set of N etch masks with 2N−
1 being less than W and 2N being greater than or equal to W, the etch masks having mask regions and spaced apart open etch regions corresponding to selected contact openings;etching, using the N etch masks, the stack of dielectric/conductive layers only through W−
1 contact openings to create extended contact openings extending to W−
1 conductive layers;the etching step comprising etching 2n−
1 conductive layers for up to half of the contact openings for each etch mask n=1, 2 . . . N;the etching step being carried out so that the contact openings are etched with different combinations of the open etch regions of said etch masks; and forming interlayer connectors in the first contact opening and the extended contact openings to electrically connect to each of the conductive layers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. An integrated circuit device comprising:
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a stack of alternating dielectric layers and electrically conductive layers including upper and lower electrically conductive layers; an overlying layer over the upper electrically conductive layer, the overlying layer having an upper surface; interlayer connectors extending from the upper surface of the overlying layer to respective ones of the electrically conductive layers to make electrical contact therewith, the interlayer connectors including first, second, third and fourth interlayer connectors; the interlayer connectors separated from one another by an average pitch; the interlayer connectors have a range of depths from greater depths to average depths to shallower depths; the first interlayer connector, having a greater depth, being adjacent to the second interlayer connector, having a shallower depth; the third and fourth interlayer connectors, having generally average depths, being adjacent to one another. - View Dependent Claims (17, 18, 19)
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Specification
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Current AssigneeMacronix International Co., Ltd.
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Original AssigneeMacronix International Co., Ltd.
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InventorsShih, Yen-Hao, Chen, Shih-Hung, Yeh, Teng-Hao, Lin, Lo-Yueh, Hu, Chih-Wei, Tsai, Feng-Nien
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Primary Examiner(s)Geyer, Scott B
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Application NumberUS13/607,555Publication NumberTime in Patent Office501 DaysField of SearchNoneUS Class Current438/598CPC Class CodesH01L 21/31116 by dry-etchingH01L 21/31144 using masksH01L 21/32137 of silicon-containing layersH01L 21/76805 the opening being a via or ...H01L 21/76816 Aspects relating to the lay...H01L 21/76831 in via holes or trenches, e...H01L 23/5226 Via connections in a multil...H01L 23/53271 containing semiconductor ma...H01L 23/5329 Insulating materialsH01L 2924/00 Indexing scheme for arrange...H01L 2924/0002 Not covered by any one of g...H10B 41/27 the channels comprising ver...H10B 41/40 characterised by the periph...H10B 41/50 characterised by the bounda...H10B 43/27 the channels comprising ver...H10B 43/40 characterised by the periph...H10B 43/50 characterised by the bounda...
