Semiconductor device and method for manufacturing the same

• US 8,633,492 B2
• Filed: 11/29/2012
• Issued: 01/21/2014
• Est. Priority Date: 10/31/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Akimoto, Kengo, Sasaki, Toshinari
• Primary Examiner(s): Lebentritt, Michael
• Application Number:
  US13/688,596
• Publication Number:
  US 20130087785A1
• Time in Patent Office: 418 Days
• Field of Search: 257/59, 257 72- 89, 257/E21.046, 257/476, 257/29.079, 257/226, 257/273
• US Class Current: 257/72
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed.

Claims

1. A semiconductor device comprising:

a gate electrode;

a gate insulating film over the gate electrode;

a first non-single crystalline oxide semiconductor layer comprising indium over the gate electrode with the gate insulating film interposed therebetween;

a second non-single crystalline oxide semiconductor layer comprising indium over the first non-single crystalline oxide semiconductor layer, the second non-single crystalline oxide semiconductor layer having an electrical conductivity lower than the first non-single crystalline oxide semiconductor layer;

a source electrode over and in electrical contact with the second non-single crystalline oxide semiconductor layer;

a drain electrode over and in electrical contact with the second non-single crystalline oxide semiconductor layer; and

an insulating film comprising silicon over the second non-single crystalline oxide semiconductor layer, the source electrode and the drain electrode,

wherein an upper surface of the second non-single crystalline oxide semiconductor layer includes a depression between the source electrode and the drain electrode so that a thickness of the second non-single crystalline oxide semiconductor layer between the source electrode and the drain electrode is smaller than thicknesses of the second non-single crystalline oxide semiconductor layer below the source electrode and the drain electrode, and

wherein the insulating film is in contact with the upper surface of the second non-single crystalline oxide semiconductor layer between the source electrode and the drain electrode.

8. The semiconductor device according to claim 1, wherein each of the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer further comprises gallium and zinc.

9. The semiconductor device according to claim 1, wherein the first non-single crystalline oxide semiconductor layer has a tapered side surface.

10. The semiconductor device according to claim 1, wherein a thickness of the first non-single crystalline oxide semiconductor layer is 1 to 50 nm.

11. The semiconductor device according to claim 1, wherein a thickness of the second non-single crystalline oxide semiconductor layer is 10 to 300 nm.

12. The semiconductor device according to claim 1, wherein each of the source electrode and the drain electrode comprises a first titanium layer, a conductive layer on the first titanium layer, and a second titanium layer on the conductive layer, the first titanium layer being in contact with the second non-single crystalline oxide semiconductor layer.

13. The semiconductor device according to claim 1, wherein the first non-single crystalline oxide semiconductor layer is thinner than the second non-single crystalline oxide semiconductor layer.

15. The semiconductor device according to claim 1, wherein the second non-single crystalline oxide semiconductor layer has a carrier concentration lower than 1×

10¹⁷/cm³.

16. The semiconductor device according to claim 1, wherein the first non-single crystalline oxide semiconductor layer has an electrical conductivity higher than 1×

10<sup>−

3</sup> S/cm.

2. A semiconductor device comprising:

a gate electrode;

a gate insulating film over the gate electrode;

a first non-single crystalline oxide semiconductor layer comprising indium over the gate electrode with the gate insulating film interposed therebetween;

a second non-single crystalline oxide semiconductor layer comprising indium over the first non-single crystalline oxide semiconductor layer, the second non-single crystalline oxide semiconductor layer having an electrical conductivity lower than the first non-single crystalline oxide semiconductor layer;

a source electrode over and in electrical contact with the second non-single crystalline oxide semiconductor layer;

a drain electrode over and in electrical contact with the second non-single crystalline oxide semiconductor layer; and

a protective film over the second non-single crystalline oxide semiconductor layer, the source electrode and the drain electrode,

wherein an upper surface of the second non-single crystalline oxide semiconductor layer includes a depression between the source electrode and the drain electrode so that a thickness of the second non-single crystalline oxide semiconductor layer between the source electrode and the drain electrode is smaller than thicknesses of the second non-single crystalline oxide semiconductor layer below the source electrode and the drain electrode, and

wherein the protective film is in contact with the upper surface of the second non-single crystalline oxide semiconductor layer between the source electrode and the drain electrode.

17. The semiconductor device according to claim 2, wherein each of the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer further comprises gallium and zinc.

24. The semiconductor device according to claim 2, wherein each of the source electrode and the drain electrode comprises a first titanium layer, a conductive layer on the first titanium layer, and a second titanium layer on the conductive layer, the first titanium layer being in contact with the second non-single crystalline oxide semiconductor layer.

29. The semiconductor device according to claim 2, wherein the first non-single crystalline oxide semiconductor layer is thinner than the second non-single crystalline oxide semiconductor layer.

3. A semiconductor device comprising:

a gate electrode;

a gate insulating film over the gate electrode;

a first non-single crystalline oxide semiconductor layer comprising indium over the gate electrode with the gate insulating film interposed therebetween;

a second non-single crystalline oxide semiconductor layer comprising indium over the first non-single crystalline oxide semiconductor layer, the second non-single crystalline oxide semiconductor layer having an electrical conductivity lower than the first non-single crystalline oxide semiconductor layer;

a source electrode over and in electrical contact with the second non-single crystalline oxide semiconductor layer;

a drain electrode over and in electrical contact with the second non-single crystalline oxide semiconductor layer; and

an insulating film comprising silicon over the second non-single crystalline oxide semiconductor layer, the source electrode and the drain electrode,

wherein part of the second non-single crystalline oxide semiconductor layer between the source electrode and the drain electrode is etched so that a portion of the second non-single crystalline oxide semiconductor layer between the source electrode and the drain electrode is thinner than portions of the second non-single crystalline oxide semiconductor layer below the source electrode and the drain electrode, and

wherein the insulating film is in contact with an upper surface of the second non-single crystalline oxide semiconductor layer between the source electrode and the drain electrode.

18. The semiconductor device according to claim 3, wherein each of the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer further comprises gallium and zinc.

22. The semiconductor device according to claim 3, wherein a thickness of the first non-single crystalline oxide semiconductor layer is 1 to 50 nm.

23. The semiconductor device according to claim 3, wherein a thickness of the second non-single crystalline oxide semiconductor layer is 10 to 300 nm.

25. The semiconductor device according to claim 3, wherein each of the source electrode and the drain electrode comprises a first titanium layer, a conductive layer on the first titanium layer, and a second titanium layer on the conductive layer, the first titanium layer being in contact with the second non-single crystalline oxide semiconductor layer.

30. The semiconductor device according to claim 3, wherein the first non-single crystalline oxide semiconductor layer is thinner than the second non-single crystalline oxide semiconductor layer.

35. The semiconductor device according to claim 3, wherein the second non-single crystalline oxide semiconductor layer has a carrier concentration lower than 1×

10¹⁷/cm³.

36. The semiconductor device according to claim 3, wherein the first non-single crystalline oxide semiconductor layer has an electrical conductivity higher than 1×

10<sup>−

3</sup> S/cm.

4. A semiconductor device comprising:

a gate electrode;

a gate insulating film over the gate electrode;

a first non-single crystalline oxide semiconductor layer comprising indium over the gate electrode with the gate insulating film interposed therebetween;

a second non-single crystalline oxide semiconductor layer comprising indium over the first non-single crystalline oxide semiconductor layer, the second non-single crystalline oxide semiconductor layer having an electrical conductivity lower than the first non-single crystalline oxide semiconductor layer;

a source electrode over and in electrical contact with the second non-single crystalline oxide semiconductor layer through a first n-type conductivity region;

a drain electrode over and in electrical contact with the second non-single crystalline oxide semiconductor layer through a second n-type conductivity region; and

an insulating film comprising silicon over the second non-single crystalline oxide semiconductor layer, the source electrode and the drain electrode,

wherein part of the second non-single crystalline oxide semiconductor layer between the source electrode and the drain electrode is etched so that a portion of the second non-single crystalline oxide semiconductor layer between the source electrode and the drain electrode is thinner than portions of the second non-single crystalline oxide semiconductor layer below the source electrode and the drain electrode,

wherein the insulating film is in contact with an upper surface of the second non-single crystalline oxide semiconductor layer between the source electrode and the drain electrode, and

wherein each of the first n-type conductivity region and the second n-type conductivity region comprises an oxide semiconductor material comprising indium.

14. The semiconductor device according to claim 4, wherein the oxide semiconductor material of each of the first n-type conductivity region and the second n-type conductivity region comprises crystals.

19. The semiconductor device according to claim 4, wherein each of the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer further comprises gallium and zinc.

27. The semiconductor device according to claim 4, wherein each of the source electrode and the drain electrode comprises a first titanium layer, a conductive layer on the first titanium layer, and a second titanium layer on the conductive layer, the first titanium layer being in contact with corresponding one of the first n-type conductivity region and the second n-type conductivity region.

31. The semiconductor device according to claim 4, wherein the first non-single crystalline oxide semiconductor layer is thinner than the second non-single crystalline oxide semiconductor layer.

5. A semiconductor device comprising:

a gate electrode;

a gate insulating film over the gate electrode;

a first non-single crystalline oxide semiconductor layer comprising indium over the gate electrode with the gate insulating film interposed therebetween;

a second non-single crystalline oxide semiconductor layer comprising indium over the first non-single crystalline oxide semiconductor layer, the second non-single crystalline oxide semiconductor layer having an electrical conductivity lower than the first non-single crystalline oxide semiconductor layer;

a source electrode over and in electrical contact with the second non-single crystalline oxide semiconductor layer through a first n-type conductivity region;

a drain electrode over and in electrical contact with the second non-single crystalline oxide semiconductor layer through a second n-type conductivity region; and

an insulating film comprising silicon over the second non-single crystalline oxide semiconductor layer, the source electrode and the drain electrode,

wherein an upper surface of the second non-single crystalline oxide semiconductor layer includes a depression between the source electrode and the drain electrode so that a thickness of the second non-single crystalline oxide semiconductor layer between the source electrode and the drain electrode is smaller than thicknesses of the second non-single crystalline oxide semiconductor layer below the source electrode and the drain electrode,

wherein the insulating film is in contact with the upper surface of the second non-single crystalline oxide semiconductor layer between the source electrode and the drain electrode,

wherein each of the first n-type conductivity region and the second n-type conductivity region comprises an oxide semiconductor material comprising indium, and

wherein the first non-single crystalline oxide semiconductor layer includes crystals.

7. The semiconductor device according to claim 5, wherein a grain size of the crystals of the first non-single crystalline oxide semiconductor layer is not larger than 10 nm.

20. The semiconductor device according to claim 5, wherein each of the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer further comprises gallium and zinc.

28. The semiconductor device according to claim 5, wherein each of the source electrode and the drain electrode comprises a first titanium layer, a conductive layer on the first titanium layer, and a second titanium layer on the conductive layer, the first titanium layer being in contact with corresponding one of the first n-type conductivity region and the second n-type conductivity region.

32. The semiconductor device according to claim 5, wherein the first non-single crystalline oxide semiconductor layer is thinner than the second non-single crystalline oxide semiconductor layer.

34. The semiconductor device according to claim 5, wherein the oxide semiconductor material of each of the first n-type conductivity region and the second n-type conductivity region comprises crystals.

6. A semiconductor device comprising:

a gate electrode;

a gate insulating film over the gate electrode;

a first non-single crystalline oxide semiconductor layer comprising indium over the gate electrode with the gate insulating film interposed therebetween;

a second non-single crystalline oxide semiconductor layer comprising indium over the first non-single crystalline oxide semiconductor layer, the second non-single crystalline oxide semiconductor layer having an electrical conductivity lower than the first non-single crystalline oxide semiconductor layer;

a source electrode over and in electrical contact with the second non-single crystalline oxide semiconductor layer;

a drain electrode over and in electrical contact with the second non-single crystalline oxide semiconductor layer;

a first insulating film comprising silicon and oxygen over the second non-single crystalline oxide semiconductor layer, the source electrode and the drain electrode;

a second insulating film comprising silicon and nitrogen over the first insulating film;

a third insulating film comprising an organic material over the second insulating film; and

a pixel electrode over the third insulating film, wherein the pixel electrode is electrically connected to one of the source electrode and the drain electrode,

wherein an upper surface of the second non-single crystalline oxide semiconductor layer includes a depression between the source electrode and the drain electrode so that a thickness of the second non-single crystalline oxide semiconductor layer between the source electrode and the drain electrode is smaller than thicknesses of the second non-single crystalline oxide semiconductor layer below the source electrode and the drain electrode, and

wherein the first insulating film is in contact with the upper surface of the second non-single crystalline oxide semiconductor layer between the source electrode and the drain electrode.

21. The semiconductor device according to claim 6, wherein each of the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer further comprises gallium and zinc.

26. The semiconductor device according to claim 6, wherein each of the source electrode and the drain electrode comprises a first titanium layer, a conductive layer on the first titanium layer, and a second titanium layer on the conductive layer, the first titanium layer being in contact with the second non-single crystalline oxide semiconductor layer.

33. The semiconductor device according to claim 6, wherein the first non-single crystalline oxide semiconductor layer is thinner than the second non-single crystalline oxide semiconductor layer.