Source/drain stack stressor for semiconductor device

• US 8,633,516 B1
• Filed: 09/28/2012
• Issued: 01/21/2014
• Est. Priority Date: 09/28/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Zhiqiang, Chang, Gwan Sin, Ching, Kuo-Cheng, Su, Chun Chung, Ju, Shi Ning
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): FOX, BRANDON C
• Application Number:
  US13/631,688
• Time in Patent Office: 480 Days
• Field of Search: 257/192, 257/331
• US Class Current: 257/192
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The present disclosure provides a semiconductor device. The device includes a substrate, a fin structure formed by a first semiconductor material, a gate region on a portion of the fin, a source region and a drain region separated by the gate region on the substrate and a source/drain stack on the source and drain region. A low portion of the source/drain stack is formed by a second semiconductor material and it contacts a low portion of the fin in the gate region. An upper portion of the source/drain stack is formed by a third semiconductor material and it contacts an upper portion of the fin in the gate region.

Claims

1. A semiconductor device comprising:

a substrate;

a fin formed by a first semiconductor material have a first lattice constant on the substrate;

a gate region formed on a portion of the fin on the substrate;

a source region and a drain region separated by the gate region on the substrate;

a source/drain stack having a thickness (T) on the source and drain region;

a second semiconductor material, having a second lattice constant, as a bottom portion of the source/drain stack and contacting a low portion of the fin in the gate region, wherein the second lattice constant is substantial smaller than the first lattice constant; and

a third semiconductor material, having a third lattice constant and a thickness (t), on top of the second semiconductor material as an upper portion of the source/drain stack and contacting an upper portion of the fin in the gate region, wherein the third lattice is larger or equal to the first lattice constant.

2. The semiconductor device of claim 1, wherein the first semiconductor material of the fin includes an epitaxial growth material.

3. The semiconductor device of claim 1, wherein the second semiconductor material of the bottom portion of the source/drain stack includes an epitaxial growth material.

4. The semiconductor device of claim 1, wherein the third semiconductor material of the upper portion of the source/drain stack includes an epitaxial growth material.

5. The semiconductor device of claim 1, wherein the second lattice constant is in a range from about 5.526 to about 5.549.

6. The semiconductor device of claim 1, wherein the third lattice constant is in a range from about 5.645 to about 5.658.

7. The semiconductor device of claim 1, wherein the thickness ratio of t to T is in a range from about 0.1 to about 0.8.

8. The semiconductor device of claim 1, wherein the fin is a germanium (Ge) fin while the source/drain stack formed by silicon germanium (SiGe) on top of Ge.

9. The semiconductor device of claim 1, wherein the fin is a silicon germanium (SiGe) fin having a first lattice constant while the source/drain stack is another SiGe having a third lattice constant on top of yet another SiGe having a second lattice constant.

10. The semiconductor device of claim 9, wherein the third lattice constant is substantially larger than the second lattice constant.

11. The semiconductor device of claim 9, wherein the third lattice constant is larger or equal to the first lattice constant.

12. A semiconductor device comprising:

a substrate having a first fin;

a second fin on top of the first fin, formed by epitaxial growth germanium (Ge);

a gate region formed on a portion of the second fin;

a source region and a drain region separated by the gate region on the substrate;

a source/drain stack having a thickness (T) on the source and drain region beside of the second Ge fin in the gate region;

an epitaxially grown silicon germanium (SiGe) as a bottom portion of the source/drain stack and contacting a lower portion of the second Ge fin; and

an epitaxially grown Ge, having a thickness (t), on top of the SiGe as an upper portion of source/drain stack and contacting an upper portion of the second Ge fin in the gate region.

13. The semiconductor device of claim 12, wherein the SiGe has a Ge composition in atomic percent in a range from about 0.45 to about 0.55.

14. The semiconductor device of claim 12, wherein a ratio of t to T is in a range from about 0.1 to about 0.8.

15. A method for fabricating a fin field-effect transistor (FinFET) device, the method comprising:

providing a substrate having first fins and isolation regions between the first fins;

recessing the first fins;

epitaxially growing a first semiconductor material having a first lattice constant to form second fin on the recessed first fins;

forming a dummy gate stack on a portion of the second fins, wherein the portion of the second fins being defined as a gate region;

recessing a portion of the second fins beside the dummy gate stack to form a source/drain region;

epitaxially growing a second semiconductor material having a second lattice constant in the source/drain region to form a lower portion of a source/drain stack and contacting a lower portion of the second fin in the gate region, where in the second lattice constant is substantial smaller than the first lattice constant; and

epitaxially growing a third semiconductor material having a third lattice constant in the source/drain region to form an upper portion of a source/drain stack and contacting an upper portion of the second fin in the gate region, where in the third lattice constant is substantial larger than the second lattice constant.

16. The method of claim 15, wherein the first lattice constant is in a range from about 5.645 to about 5.658.

17. The method of claim 15, wherein the second lattice constant is in a range from about 5.526 to about 5.549.

18. The method of claim 15, wherein the third lattice constant is larger or equal to the first lattice constant.

19. The method of claim 15, wherein a thickness ratio of the third semiconductor material to the source/drain stack is in a range from about 0.1 to 0.8.

20. The method of claim 15, further comprising:

removing the dummy gate stack to form a gate trench; and

forming a high-k/metal gate in the gate trench.