Semiconductor device and method of manufacturing the same

• US 8,633,530 B2
• Filed: 10/23/2009
• Issued: 01/21/2014
• Est. Priority Date: 01/15/2009
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Funayama, Kota, Chakihara, Hiraku, Ishii, Yasushi
• Primary Examiner(s): Lam, Cathy N
• Application Number:
  US13/144,744
• Publication Number:
  US 20110272753A1
• Time in Patent Office: 1,551 Days
• Field of Search: 257/299, 257/E29.309, 257/E27.016, 257/E21.421, 257/324, 257/325, 428/591, 428/239, 428/283
• US Class Current: 257/299
• CPC Class Codes: H01L 23/53214 the principal metal being aluminium
• CPC Class Codes: H01L 23/53257 the principal metal being a refractory metal
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.

Claims

1. A semiconductor device having a memory cell,

wherein the memory cell comprises:

a first gate insulating film made of a first insulating film formed on a semiconductor substrate;

a selection gate electrode made of a first conductive film formed on the first gate insulating film;

a cap insulating film made of a second insulating film formed on the selection gate electrode;

a memory gate electrode made of a second conductive film formed in a sidewall shape on one side surface of a stacked film made up of the cap insulating film and the selection gate electrode; and

a second gate insulating film formed between the stacked film made up of the cap insulating film and the selection gate electrode and the memory gate electrode and formed also between the memory gate electrode and the semiconductor substrate,

in a region in which a first plug supplying a voltage to the memory gate electrode is formed, an interlayer insulating film made of a third insulating film is provided on the semiconductor substrate, the cap insulating film and the memory gate electrode, and

the first plug formed by embedding a third conductive film in a first contact hole formed in the interlayer insulating film is formed so as to be electrically connected to the memory gate electrode and cover a part of the cap insulating film.

2. The semiconductor device according to claim 1,

wherein the cap insulating film is made of silicon nitride, silicon oxide, silicon oxide containing nitrogen or silicon carbide.

3. The semiconductor device according to claim 1,

wherein the second gate insulating film is formed of a stacked film made up of a fourth insulating film, a charge accumulating layer formed on the fourth insulating film and a fifth insulating film formed on the charge accumulating layer.

4. The semiconductor device according to claim 3,

wherein the charge accumulating layer is made of silicon nitride.

5. The semiconductor device according to claim 1,

wherein a MISFET is formed around the memory cell, and

the MISFET includes:

a third gate insulating film made of the first insulating film formed on the semiconductor substrate; and

a gate electrode formed on the third gate insulating film and made of the first conductive film.

6. The semiconductor device according to claim 1,

wherein, in a region in which a second plug supplying a voltage to the selection gate electrode is formed, the cap insulating film is removed, and the second plug formed by embedding the third conductive film in a second contact hole formed in the interlayer insulating film is electrically connected to a silicide layer formed on an upper surface of the selection gate electrode.

7. The semiconductor device according to claim 1,

wherein, in a region in which the memory cell is formed, a height of the selection gate electrode from a main surface of the semiconductor substrate is lower than a height of the memory gate electrode from the main surface of the semiconductor substrate.

8. The semiconductor device according to claim 1,

wherein a height of the memory gate electrode from a main surface of the semiconductor substrate in a region in which the memory cell is formed and in the region in which the first plug supplying a voltage to the memory gate electrode is formed is higher than a height of the memory gate electrode from the main surface of the semiconductor substrate in the region in which a second plug supplying a voltage to the selection gate electrode is formed.

9. The semiconductor device according to claim 1,

wherein, in the region in which the first plug supplying the voltage to the memory gate electrode is formed and in a region in which a second plug supplying a voltage to the selection gate electrode is formed, a device isolation part made of an insulating film is formed in the semiconductor substrate.

10. The semiconductor device according to claim 1,

wherein the memory cell further comprises a drain region in the semiconductor substrate on a side of the selection gate electrode opposite to the memory gate electrode,

in a region in which the memory cell is formed, the interlayer insulating film made of the third insulating film is provided on the semiconductor substrate, the cap insulating film and the memory gate electrode, and a third plug formed by embedding the third conductive film in a third contact hole formed in the interlayer insulating film is electrically connected to the drain region, and

the third plug is formed also on the cap insulating film.

11. The semiconductor device according to claim 10,

wherein two of the memory cells sharing the drain region are symmetrically disposed in a channel direction, and

the third plug is formed on the cap insulating films of both of the two memory cells.

12. The semiconductor device according to claim 10,

wherein a planar shape of the third contact hole is an ellipse or a true circle.

13. The semiconductor device according to claim 10,

wherein a silicide layer is formed on the drain region, and the third plug is connected to the silicide layer.

14. The semiconductor device according to claim 1,

wherein, in a region in which the memory cell is formed and in the region in which the first plug supplying the voltage to the memory gate electrode is formed, a thermal oxidation film made of a sixth insulating film is formed between the selection gate electrode and the cap insulating film.

15. The semiconductor device according to claim 14,

wherein the sixth insulating film is made of silicon oxide.