Semiconductor device and fabrication method thereof

• US 8,633,549 B2
• Filed: 10/06/2011
• Issued: 01/21/2014
• Est. Priority Date: 10/06/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Chieh-Te, Tzou, Shih-Fang, Liao, Jiunn-Hsiung, Lin, Yi-Po
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): Vuong, Thai T
• Application Number:
  US13/267,068
• Publication Number:
  US 20130087861A1
• Time in Patent Office: 838 Days
• Field of Search: 257/379, 257/E27.071, 257/E21.616, 438/238
• US Class Current: 257/379
• CPC Class Codes: H01L 21/027 Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 photographic masks or originals per se G03F1/00; registration or positioning of photographic masks or originals G03F9/00; photographic cameras G03B; control of position G05D3/00
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/8232 Field-effect technology
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors

Abstract

A semiconductor device comprises a metal gate electrode, a passive device and a hard mask layer. The passive device has a poly-silicon element layer. The hard mask layer is disposed on the metal gate electrode and the passive electrode and has a first opening and a second opening substantially coplanar with each other, wherein the metal gate electrode and the poly-silicon element layer are respectively exposed via the first opening and the second opening; and there is a distance between the first opening and the metal gate electrode substantially less than the distance between the second opening and the poly-silicon element layer.

Claims

1. A semiconductor device comprising:

a metal gate electrode,

a passive device, having a dielectric material layer, a poly-silicon element layer disposed on the dielectric material layer and a capping layer disposed between the poly-silicon element layer and the dielectric material layer; and

a hard mask layer covered on the metal gate electrode and the passive electrode and having a first opening and a second opening substantially coplanar with each other, wherein there is a height difference between a top surface of the metal gate electrode and a top surface of the poly-silicon element layer.

2. The semiconductor device according to claim 1, further comprising:

a substrate;

a source/drain structure, formed in the substrate and adjacent to the metal gate electrode; and

a gate dielectric layer, disposed between the metal gate electrode and the source/drain structure.

3. The semiconductor device according to claim 2, wherein the gate dielectric layer comprises an interfacial layer (IL) and a high-k dielectric layer.

4. The semiconductor device according to claim 3, further comprising a capping layer disposed between the metal gate electrode and the high-k dielectric layer.

5. The semiconductor device according to claim 1, wherein the passive device is an electrical resistor.

6. The semiconductor device according to claim 1, further comprising:

a first spacer, comprising a portion of the hard mask layer covered on sidewalls of the metal gate electrode used to defined the first opening; and

a second spacer, comprising another portion of the hard mask layer covered on the poly-silicon element layer used to defined the second opening.

7. The semiconductor device according to claim 1, wherein the capping layer is made of titanium nitride (TiN) or tantalum nitride (TaN).