Circuits and related techniques for driving a high side of a half bridge circuit

• US 8,633,745 B1
• Filed: 08/30/2012
• Issued: 01/21/2014
• Est. Priority Date: 08/30/2012
• Status: Active Grant

• Current Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Original Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Inventors: Peterson, Douglas
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US13/599,211
• Time in Patent Office: 509 Days
• Field of Search: 327108-111
• US Class Current: 327/156
• CPC Class Codes: H03K 17/08104 in field-effect transistor switches H03K17/0812, H03K17/0814 take precedence
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A level shift circuit is configured to control a high side transistor of a half bridge circuit. The level shift circuit has composite current mirrors and other circuits that reduce the effect of transient voltages that are produced as the half bridge circuit is switched.

Claims

1. An electronic circuit for driving an N-type transistor, the N-type transistor having a control node, an output node, and a power supply node coupled to a high voltage supply, the electronic circuit comprising:

a bootstrap voltage node capacitively coupled to the output node of the N-type transistor;

a first input transistor having a control node, a current input node, and a current output node, wherein the control node is coupled to receive a first input signal;

a second input transistor having a control node, a current input node, and a current output node, wherein the control node is coupled to receive a second input signal;

a first composite current mirror circuit having a control node, a current input node, and a current output node, wherein the control node of the first composite current mirror circuit is coupled to the current input node of the first input transistor, and wherein the current input node of the first composite current mirror circuit is coupled to the bootstrap voltage node;

a second composite current mirror circuit having a control node, a current input node, and a current output node, wherein the control node of the second composite current mirror circuit is coupled to the current input node of the second input transistor, and wherein the current input node of the second composite current mirror circuit is coupled to the bootstrap voltage node;

a first comparator having a first input node coupled to the current output node of the second composite current mirror circuit and having a second input node coupled to receive a first reference voltage, wherein the first reference voltage is related to a voltage at the output node of the N-type transistor, wherein the first comparator also has an output node; and

a second comparator having a first input node coupled to the output node of the first composite current mirror circuit and having a second input node coupled to receive a second reference voltage, wherein the second reference voltage is related to the voltage at the output node of the N-type transistor, wherein the second comparator also has an output node.

2. The electronic circuit of claim 1, wherein the first composite current mirror circuit comprises:

a first current mirror having a control node, a current input node, and a current output node, wherein the control node of the first current mirror is coupled to the current input node of the first input transistor, and wherein the current input node of the first current mirror is coupled to the bootstrap voltage node;

a second current mirror having a control node, a current input node, and a current output node, wherein the control node of the second current mirror is coupled to the current output node of the first current mirror, and wherein the current output node of the second current mirror is coupled to the output node of the N-type transistor; and

a third current mirror having a control node, a current input node, and a current output node, wherein the control node of the third current mirror is coupled to the current input node of the second current mirror, wherein the current input node of the third current mirror is coupled to the bootstrap voltage node, and wherein the current output node of the third current mirror is coupled to the first input node of the second comparator, and wherein the second composite current mirror circuit comprises;

a fourth current mirror having a control node, a current input node, and a current output node, wherein the control node of the fourth current mirror is coupled to the current input node of the second input transistor, and wherein the current input node of the fourth current mirror is coupled to the bootstrap voltage node,

a fifth current mirror having a control node, a current input node, and a current output node, wherein the control node of the fifth current mirror is coupled to the current output node of the fourth current mirror, and wherein the current output node of the fifth current mirror is coupled to the output node of the N-type transistor; and

a sixth current mirror having a control node, a current input node, and a current output node, wherein the control node of the sixth current mirror is coupled to the current input node of the fifth current mirror, wherein the current input node of the sixth current mirror is coupled to the bootstrap voltage node, and wherein the current output node of the sixth current mirror is coupled to the first input node of the first comparator.

3. The electronic circuit of claim 2, wherein the second current mirror further has a second current input node, wherein the second current input node of the second current mirror is coupled to the first input node of the first comparator, wherein the fifth current mirror further has a second current input node, and wherein the second current input node of the fifth current mirror is coupled to the first input node of the second comparator.

4. The electronic circuit of claim 3, wherein the N-type transistor is a first N-type transistor and is coupled to a second N-type transistor.

5. The electronic circuit of claim 3, wherein the first input signal is a reset input signal, and wherein the second input signal is a set input signal, wherein a voltage at the output node of the first comparator achieves a high state in response to a positive pulse in the set input signal, and wherein the voltage of the output node of the second comparator achieves a high state in response to a positive pulse in the reset input signal.

6. The electronic circuit of claim 5, further comprising:

a first current generator coupled between the output node of the N-Type transistor and the first input node of the first comparator; and

a second current generator coupled between the output node of the N-Type transistor and the first input node of the second comparator.

7. The electronic circuit of claim 6, further comprising:

a first voltage to voltage converter having first and second input nodes and first and second output nodes, wherein the first input node of the first voltage to voltage converter is coupled to the current output node of the second composite current mirror circuit, and wherein the second input node of the first voltage to voltage converter is coupled to receive the first reference voltage; and

a second voltage to voltage converter having first and second input nodes and first and second output nodes, wherein the first input node of the second voltage to voltage converter is coupled to the current output node of the first composite current mirror circuit, and wherein the second input node of the second voltage to voltage converter is coupled to receive the second reference voltage.

8. The electronic circuit of claim 7, further comprising:

a first low pass filter having an input node and an output node, wherein the output node of the first low pass filter is coupled to the first input node of the first comparator, wherein the input node of the first low pass filter is coupled to the first output node of the first voltage to voltage converter, and wherein the second input node of the first comparator is coupled to the second output node of the first voltage to voltage converter; and

a second low pass filter having an input node and an output node, wherein the output node of the second low pass filter is coupled to the first input node of the second comparator, wherein the input node of the second low pass filter is coupled to the first output node of the second voltage to voltage converter, and wherein the second input node of the second comparator, is coupled to the second output node of the second voltage to voltage converter.

9. The electronic circuit of claim 6, further comprising:

a first low pass filter having an input node and an output node, wherein the input node of the first low pass filter is coupled to the output node of the first comparator,

a second low pass filter having an input node and an output node, wherein the input node of the second low pass filter is coupled to the output node of the second comparator.

10. The electronic circuit of claim 9, wherein the second current mirror further has a third current input node and a fourth current input node, and wherein the fifth current mirror further has a third current input node coupled to the third current input node of the second current mirror and a fourth current input node coupled to the fourth current input node of the second current mirror.

11. The electronic circuit of claim 10, wherein the first comparator comprises:

a first comparator current mirror having a control node, a current input node, and a current output node, wherein the control node of the first comparator current mirror is coupled to receive a first speed signal from the third current input nodes of the second and fifth current mirrors that results in the first comparator achieving a higher output signal slew rate during a predetermined condition of the first speed signal; and

wherein the second comparator comprises;

a second comparator current mirror having a control node, a current input node, and a current output node, wherein the control node of the second comparator current mirror is coupled to receive a first speed signal from the fourth current input node of the second and fifth current mirrors that results in the second comparator achieving a higher output signal slew rate during a predetermined condition of the second speed signal.

12. The electronic circuit of claim 3, wherein the first input signal is a set input signal, and wherein the second input signal is a reset input signal, wherein a voltage at the output node of the first comparator achieves a high state in response to a positive pulse in the set input signal, and wherein the voltage of the output node of the second comparator achieves a high state in response to a positive pulse in the reset input signal.

13. The electronic circuit of claim 12, further comprising:

a first current generator coupled between the bootstrap voltage node and the first input node of the first comparator; and

a second current generator coupled between the bootstrap voltage node and the first input node of the second comparator.

14. The electronic circuit of claim 13, further comprising:

a first voltage to voltage converter having first and second input nodes and first and second output nodes, wherein the first input node of the first voltage to voltage converter is coupled to the current output node of the second composite current mirror circuit, and wherein the second input node of the first voltage to voltage converter is coupled to receive the first reference voltage; and

a second voltage to voltage converter having first and second input nodes and first and second output nodes, wherein the first input node of the second voltage to voltage converter is coupled to the current output node of the first composite current mirror circuit, and wherein the second input node of the second voltage to voltage converter is coupled to receive the second reference voltage.

15. The electronic circuit of claim 14, further comprising:

a first low pass filter having an input node and an output node, wherein the output node of the first low pass filter is coupled to the first input node of the first comparator, wherein the input node of the first low pass filter is coupled to the first output node of the first voltage to voltage converter, and wherein the second input node of the first comparator is coupled to the second output node of the first voltage to voltage converter; and

a second low pass filter having an input node and an output node, wherein the output node of the second low pass filter is coupled to the first input node of the second comparator, wherein the input node of the second low pass filter is coupled to the first output node of the second voltage to voltage converter, and wherein the second input node of the second comparator, is coupled to the second output node of the second voltage to voltage converter.

16. The electronic circuit of claim 13, further comprising:

a first low pass filter having an input node and an output node, wherein the input node of the first low pass filter is coupled to the output node of the first comparator,

a second low pass filter having an input node and an output node, wherein the input node of the second low pass filter is coupled to the output node of the second comparator.

17. The electronic circuit of claim 16, wherein the second current mirror further has a third current input node and a fourth current input node, and wherein the fifth current mirror further has a third current input node coupled to the third current input node of the second current mirror and a fourth current input node coupled to the fourth current input node of the second current mirror.

18. The electronic circuit of claim 17, wherein the first comparator comprises:

a first comparator current mirror having a control node, a current input node, and a current output node, wherein the control node of the first comparator current mirror is coupled to receive a first speed signal from the third current input nodes of the second and fifth current mirrors that results in the first comparator achieving a higher output signal slew rate during a predetermined condition of the first speed signal; and

wherein the second comparator comprises;

a second comparator current mirror having a control node, a current input node, and a current output node, wherein the control node of the second comparator current mirror is coupled to receive a first speed signal from the fourth current input node of the second and fifth current mirrors that results in the second comparator achieving a higher output signal slew rate during a predetermined condition of the second speed signal.

19. The electronic circuit of claim 1, wherein the first comparator comprises:

a first comparator current mirror having a control node, a current input node, and a current output node, wherein the control node of the first comparator current mirror is coupled to receive a first speed signal that results in the first comparator achieving a higher output signal slew rate during a predetermined condition of the speed signal; and

wherein the second comparator comprises;

a second comparator current mirror having a control node, a current input node, and a current output node, wherein the control node of the second comparator current mirror is coupled to receive a second speed signal that results in the second comparator achieving a higher output signal slew rate during a predetermined condition of the second speed signal.

20. The electronic circuit of claim 1, wherein the first composite current mirror circuit comprises:

a first current mirror having a control node, a current input node, and first and second current output nodes, wherein the control node of the first current mirror is coupled to the current input node of the first input transistor, and wherein current input node of the first current mirror is coupled to the bootstrap voltage node; and

a second current mirror having a control node, a current input node, a current output node, wherein the control node of the second current mirror is coupled to the first current output node of the first current mirror, and wherein the current input node of the second current mirror is coupled to the first input node of the first comparator, and wherein the second composite current mirror circuit comprises;

a third current mirror having a control node, a current input node, and first and second current output nodes current output node, wherein the control node of the third current mirror is coupled to the current input node of the second input transistor, and wherein the current input node of the fourth current mirror is coupled to the bootstrap voltage node; and

a fourth current mirror having a control node, a current input node, and a current output node, wherein the control node of the fourth current mirror is coupled to the first current output node of the third current mirror, and wherein the current input node of the fourth current mirror is coupled to the first input node of the second comparator, wherein

the second current output node of the first current mirror is coupled to the current input node of the fourth current mirror, and wherein

the second current output node of the third current mirror is coupled to the current input node of the second current mirror.