Driving method of semiconductor device

• US 8,634,228 B2
• Filed: 08/29/2011
• Issued: 01/21/2014
• Est. Priority Date: 09/02/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Matsuzaki, Takanori, Kato, Kiyoshi
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US13/220,066
• Publication Number:
  US 20120063203A1
• Time in Patent Office: 876 Days
• Field of Search: 365/149, 365/189.04, 365/185.1, 365/185.01, 365/104
• US Class Current: 365/149
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell

Abstract

A driving method of a semiconductor device is provided. In a semiconductor device including a bit line, a selection line, a selection transistor, m (m is a natural number greater than or equal to 2) writing word lines, m reading word lines, a source line, and first to m-th memory cells, each memory cell includes a first transistor and a second transistor that holds charge accumulated in a capacitor. The second transistor includes a channel formed in an oxide semiconductor layer. In a driving method of a semiconductor device having the above structure, when writing to a memory cell is performed, the first transistor is turned on so that a first source terminal or a first drain terminal is set to a fixed potential; thus, a potential is stably written to the capacitor.

Claims

1. A driving method of a semiconductor device, the semiconductor device comprising:

a memory cell comprising a first transistor, a capacitor and a second transistor, wherein a gate of the first transistor is electrically connected to one electrode of the capacitor and a source of the second transistor;

a selection transistor, wherein a source of the selection transistor is electrically connected to a drain of the first transistor and a drain of the selection transistor is electrically connected to a drain of the second transistor;

a bit line electrically connected to a drain of the selection transistor and the drain of the second transistor;

a selection line electrically connected to a gate of the selection transistor;

a writing word line electrically connected to a gate of the second transistor;

a reading word line electrically connected to the other electrode of the capacitor; and

a source line electrically connected to a source of the first transistor,

the driving method comprising the steps of;

supplying a potential to the bit line;

supplying a potential to the writing word line to turn on the second transistor, whereby a potential is supplied to the one electrode of the capacitor from the bit line;

supplying a potential to the selection line to turn off the selection transistor; and

supplying a potential to the source line to turn on the first transistor, whereby a charge corresponding to the potential to the bit line is accumulated in the gate of the first transistor and the one electrode of the capacitor,

wherein the potential to the source line is lower than a threshold value of the first transistor to turn on the first transistor.

2. The driving method of a semiconductor device according to claim 1, wherein the potential of the source of the first transistor is set to a fixed potential.

3. The driving method of a semiconductor device according to claim 1, further comprising steps of:

supplying a potential to the writing word line to turn off the second transistor; and

supplying a potential to the source line to turn off the first transistor, whereby the charge corresponding to the potential to the bit line is held in the gate of the first transistor and the one electrode of the capacitor.

4. The driving method of a semiconductor device according to claim 1, wherein the second transistor is formed using an oxide semiconductor material comprising In, Ga, and Zn.

5. The driving method of a semiconductor device according to claim 1, wherein the first transistor includes single crystal silicon.

6. A driving method of a semiconductor device, the semiconductor device comprising:

a memory cell comprising a first transistor, a capacitor and a second transistor, wherein a gate of the first transistor is electrically connected to one electrode of the capacitor and a source of the second transistor;

a selection transistor, wherein a source of the selection transistor is electrically connected to a drain of the first transistor and a drain of the selection transistor is electrically connected to a drain of the second transistor;

a bit line electrically connected to a drain of the selection transistor and the drain of the second transistor;

a selection line electrically connected to a gate of the selection transistor;

a writing word line electrically connected to a gate of the second transistor;

a reading word line electrically connected to the other electrode of the capacitor; and

a source line electrically connected to a source of the first transistor,

the driving method comprising the steps of;

supplying a potential to the selection line to turn off the selection transistor;

supplying a potential to the source line to turn on the first transistor;

supplying a potential to the bit line; and

supplying a potential to the writing word line to turn on the second transistor, whereby a potential is supplied to the one electrode of the capacitor from the bit line and a charge corresponding to the potential to the bit line is accumulated in the gate of the first transistor and the one electrode of the capacitor,

wherein the potential to the source line is lower than a threshold value of the first transistor to turn on the first transistor.

7. The driving method of a semiconductor device according to claim 6, wherein the potential of the source of the first transistor is set to a fixed potential.

8. The driving method of a semiconductor device according to claim 6, further comprising steps of:

supplying a potential to the writing word line to turn off the second transistor; and

supplying a potential to the source line to turn off the first transistor, whereby the charge corresponding to the potential to the bit line is held in the gate of the first transistor and the one electrode of the capacitor.

9. The driving method of a semiconductor device according to claim 6, wherein the second transistor is formed using an oxide semiconductor material comprising In, Ga, and Zn.

10. The driving method of a semiconductor device according to claim 6, wherein the first transistor includes single crystal silicon.

11. A driving method of a semiconductor device, the semiconductor device comprising:

first to m-th memory cells,

wherein each of the first to m-th memory cells comprises a first transistor, a capacitor, and a second transistor,

wherein a gate of the first transistor is electrically connected to one electrode of the capacitor and a source of the second transistor,

wherein a drain of the first transistor of a k-th memory cell (k is a natural number greater than or equal to 2 and less than or equal to (m−

1)) is electrically connected to a source of the first transistor of a (k−

1)-th memory cell, and

wherein a source of the first transistor of the k-th memory cell is electrically connected to a drain of the first transistor of a (k+1)-th memory cell;

a selection transistor, wherein a source of the selection transistor is electrically connected to a drain of the first transistor of the first memory cell and a drain of the selection transistor is electrically connected to a drain of the second transistor of the first memory cell;

a bit line electrically connected to a drain of the selection transistor and the drain of the second transistor of the first memory cell;

a selection line electrically connected to a gate of the selection transistor;

first to m-th writing word lines, wherein a j-th writing word line (j is a natural number greater than or equal to 1 and less than or equal to m) is electrically connected to a gate of the second transistor of a j-th memory cell;

first to m-th reading word lines, wherein a j-th reading word line is electrically connected to the other electrode of the capacitor of the j-th memory cell; and

a source line electrically connected to a source of the first transistor of the m-th memory cell,

the driving method comprising the steps of;

supplying a potential to the bit line;

supplying a potential to the writing word line to turn on the second transistor, whereby a potential is supplied to the one electrode of the capacitor from the bit line;

supplying a potential to the selection line to turn off the selection transistor;

supplying a potential to the source line to turn on the first transistor, whereby a charge corresponding to the potential to the bit line is accumulated in the gate of the first transistor and the one electrode of the capacitor;

supplying a potential to the writing word line to turn off the second transistor; and

supplying a potential to the source line to turn off the first transistor, whereby the charge corresponding to the potential to the bit line is held in the gate of the first transistor and the one electrode of the capacitor,

wherein the potential to the source line is lower than a threshold value of the first transistor to turn on the first transistor.

12. The driving method of a semiconductor device according to claim 11, wherein the potential of the source of the first transistor is set to a fixed potential.

13. The driving method of a semiconductor device according to claim 11, wherein the second transistor is formed using an oxide semiconductor material comprising In, Ga, and Zn.

14. A driving method of a semiconductor device, the semiconductor device comprising:

first to m-th memory cells,

wherein each of the first to m-th memory cells comprises a first transistor, a capacitor, and a second transistor,

wherein a gate of the first transistor is electrically connected to one electrode of the capacitor and a source of the second transistor,

wherein a drain of the first transistor of a k-th memory cell (k is a natural number greater than or equal to 2 and less than or equal to (m−

1)) is electrically connected to a source of the first transistor of a (k−

1)-th memory cell, and

wherein a source of the first transistor of the k-th memory cell is electrically connected to a drain of the first transistor of a (k+1)-th memory cell;

a selection transistor, wherein a source of the selection transistor is electrically connected to a drain of the first transistor of the first memory cell and a drain of the selection transistor is electrically connected to a drain of the second transistor of the first memory cell;

a bit line electrically connected to a drain of the selection transistor and the drain of the second transistor of the first memory cell;

a selection line electrically connected to a gate of the selection transistor;

first to m-th writing word lines, wherein a j-th writing word line (j is a natural number greater than or equal to 1 and less than or equal to m) is electrically connected to a gate of the second transistor of a j-th memory cell;

first to m-th reading word lines, wherein a j-th reading word line is electrically connected to the other electrode of the capacitor of the j-th memory cell; and

a source line electrically connected to a source of the first transistor of the m-th memory cell,

the driving method comprising the steps of;

supplying a potential to the selection line to turn off the selection transistor;

supplying a potential to the source line to turn on the first transistor;

supplying a potential to the bit line;

supplying a potential to the writing word line to turn on the second transistor, whereby a potential is supplied to the one electrode of the capacitor from the bit line and a charge corresponding to the potential to the bit line is accumulated in the gate of the first transistor and the one electrode of the capacitor;

supplying a potential to the writing word line to turn off the second transistor; and

supplying a potential to the source line to turn off the first transistor, whereby the charge corresponding to the potential to the bit line is held in the gate of the first transistor and the one electrode of the capacitor,

wherein the potential to the source line is lower than a threshold value of the first transistor to turn on the first transistor.

15. The driving method of a semiconductor device according to claim 14, wherein the potential of the source of the first transistor is set to a fixed potential.

16. The driving method of a semiconductor device according to claim 14, wherein the second transistor is formed using an oxide semiconductor material comprising In, Ga, and Zn.