Non-volatile memory and method with accelerated post-write read to manage errors
First Claim
1. A method of operating a non-volatile memory, comprising:
- providing multiple groups of memory cells, the memory cells in each group for operating in parallel;
programming an original copy of multiple subsets of data into a first group of memory cells, each subset of data being provided with an ECC;
performing a post write read of the first group of memory cells by;
selecting a sample of the first group of memory cells corresponding to a subset of data with associated ECC;
checking said sample for errors by processing with the associated ECC, andreprogramming said original copy of multiple subsets of data into a second group of memory cells whenever the errors checked from the sample is more than a predetermined number of error bits, and wherein the first and second groups of memory cells each forms a block of memory cells that is a minimum erase unit.
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Abstract
Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. An error management provides reading and checking the copy after copying to the second portion. If the copy has excessive error bits, it is repeated in a different location either in the second or first portion. The reading and checking of the copy is accelerated by reading only a sample of it. The sample is selected from a subset of the copy having its own ECC and estimated to represent a worst error rate among the copy it is sampling. One embodiment has the sample taken from one bit of each multi-bit memory cell of a group.
70 Citations
18 Claims
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1. A method of operating a non-volatile memory, comprising:
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providing multiple groups of memory cells, the memory cells in each group for operating in parallel; programming an original copy of multiple subsets of data into a first group of memory cells, each subset of data being provided with an ECC; performing a post write read of the first group of memory cells by; selecting a sample of the first group of memory cells corresponding to a subset of data with associated ECC; checking said sample for errors by processing with the associated ECC, and reprogramming said original copy of multiple subsets of data into a second group of memory cells whenever the errors checked from the sample is more than a predetermined number of error bits, and wherein the first and second groups of memory cells each forms a block of memory cells that is a minimum erase unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A non-volatile memory, comprising:
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multiple groups of memory cells, the memory cells in each group for operating in parallel; a programming circuit for programming an original copy of multiple subsets of data into a first group of memory cells, each subset of data being provided with an ECC; a sample of the data programmed in the first group of memory cells, the sample being a subset of data among said multiple subsets of data programmed into the first group; a reading circuit for reading said sample including an associated ECC; an ECC decoder for performing a post write read to check said programming by checking errors in said sample by processing with the associated ECC, and a reprogramming circuit for reprogramming said original copy of multiple subsets of data into a second group of memory cells whenever the errors checked from the sample is more than a predetermined number of error bits, and wherein the first and second groups of memory cells each forms a block of memory cells that is a minimum erase unit. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification