NAND flash based content addressable memory

• US 8,634,247 B1
• Filed: 01/24/2013
• Issued: 01/21/2014
• Est. Priority Date: 11/09/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Sprouse, Steven T., Li, Yan
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US13/749,361
• Time in Patent Office: 362 Days
• Field of Search: 36518501-18533
• US Class Current: 365/185.17
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 15/046 using non-volatile storage elements
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor

Abstract

A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so on. A host writes a key-value pair to the drive, where the drive writes the keys along bit lines of a CAM NAND portion of the drive and stores the value in the drive. The drive then maintains a table linking the keys to location of the value. In a read process, the host provides a key to drive, which then broadcasts down the word lines of blocks storing the keys. Based on any matching bit lines, the tables can then be used to retrieve and supply the corresponding data to the host.

Claims

1. A memory circuit, comprising:

an array of non-volatile memory cells arranged into a NAND type of architecture, including a plurality of M NAND strings, each having a plurality of N memory cells connected in series, and a plurality of N word lines spanning the M NAND strings, each of the N word lines connected to a corresponding one of the N memory cells thereof, where M and N are integers;

word line driving circuitry connectable to the second plurality of word lines, whereby each of N word lines can be concurrently and individually be set to one of a plurality of data dependent read values corresponding to a data pattern; and

sensing circuitry connectable to the M NAND strings to individually determine those of the M NAND strings that are conducting in response the word line driving circuitry applying a data pattern to the N word lines.

2. The memory circuit of claim 1, wherein the memory cells are EEPROM devices.

3. The memory circuit of claim 1, wherein the memory array is of a 3D-type of memory structure.

4. The memory circuit of claim 1, wherein the memory cells are operated as binary devices.

5. The memory circuit of claim 1, wherein the memory cells are operated as multi-state devices.

6. The memory circuit of claim 1, wherein the memory array is operated to include both binary and multi-state devices along the same NAND string, a first subset of the N word lines spanning memory cells operated in a binary mode and a second subset of the N word lines spanning memory cells operated in a multi-state mode.

7. The memory circuit of claim 1, wherein the M NAND strings each include one or more additional memory cells connected in series with the N memory cells thereof.

8. The memory circuit of claim 1, wherein the word line driving circuitry can apply a first data pattern to the N word lines and subsequently apply a second data pattern to the N word lines, wherein the word line driving circuitry obtains the second data pattern by inverting one or more of the read values the first data pattern.

9. The memory circuit of claim 8, wherein the data pattern includes one or more values corresponding to data values to be ignored, and wherein the second data pattern inverts all of the read values of the first data pattern except values to be ignored.

10. The memory circuit of claim 8, wherein the sensing circuitry can compare the NAND strings that conduct in response to the first data pattern with those that conduct in response to the second data pattern.

11. The memory circuit of claim 1, further comprising:

programming circuitry connectable to the word lines and NAND strings to write data into the memory cells of a selected word line.

12. The memory circuit of claim 11, wherein the programming circuitry includes data latches for holding data content to be written into memory cells of a selected word line, wherein subsequent to writing the data content held in the latches along a first selected word line, the data content can be inverted for writing in inverted form into a second selected word line.

13. The memory circuit of claim 11, wherein the programming circuitry includes data latches for holding data content to be written into memory cells of a selected word line, wherein data received and stored at a corresponding latch to be written into each of ½

M of the NAND strings along a selected word line is stored in inverted form in a corresponding latch to be written in inverted form in an associated one of the other ½

M of the NAND strings along the selected word line.