On-device data analytics using NAND flash based intelligent memory

• US 8,634,248 B1
• Filed: 01/31/2013
• Issued: 01/21/2014
• Est. Priority Date: 11/09/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Sprouse, Steven T., Li, Yan, George, Johann
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US13/756,131
• Time in Patent Office: 355 Days
• Field of Search: 36518501-18533
• US Class Current: 365/185.17
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 15/046 using non-volatile storage elements
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor

Abstract

A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so on. A host writes a key-value pair to the drive, where the drive writes the keys along bit lines of a CAM NAND portion of the drive and stores the value in the drive. The drive then maintains a table linking the keys to location of the value. In a read process, the host provides a key to drive, which then broadcasts down the word lines of blocks storing the keys. Based on any matching bit lines, the tables can then be used to retrieve and supply the corresponding data to the host. The system can be applied to perform a wide range of analytics on data sets loaded into the NAND array.

Claims

1. A method of operating a non-volatile array of a NAND architecture, the array having NAND strings formed along bit lines and spanned by word lines, where the bit lines span a plurality of the blocks and are each connected to a corresponding set of latches, the method comprising:

reading a first page of data from a first word line of the array;

storing the first page of data in a first of the latches for each of the bit lines of the array;

reading a second page of data from a second word line of the array, the first and second of the word lines being different;

storing the second page of data in a second of the latches for each of the bit lines of the array, wherein the first and second latches for each of the bit lines are different;

performing within said sets of latches one or more arithmetical/logical operations upon the contents of the first and second latches;

subsequently to performing said one or more arithmetical/logical operations, writing the result thereof from the sets of latches along a third word line of the array.

2. The method of claim 1, wherein said performing within said sets of latches one or more arithmetical/logical operations upon the contents of the first and second latches includes:

using a third latch for each of the bit lines of the array for carry operations, wherein the first, second and third latches for each of the bit lines are different.

3. The method of claim 1, further comprising:

writing the result of the one or more arithmetical/logical operations back to one or either the first and second latches for use in said writing result thereof.

4. The method of claim 1, wherein said one or more arithmetical/logical operations includes adding the contents of the first and second latches.

5. The method of claim 1, wherein said one or more arithmetical/logical operations includes subtracting the contents of the first and second latches.

6. The method of claim 1, wherein said one or more arithmetical/logical operations includes multiplying the contents of the first and second latches.

7. The method of claim 1, wherein said one or more arithmetical/logical operations includes dividing the contents of the first and second latches.

8. The method of claim 1, where the array is formed of multiple blocks of NAND strings formed along the bit lines, and wherein the third word line is from a different block that the first and second word lines.

9. The method of claim 8, wherein the first and second word lines are from different blocks.

10. The method of claim 8, wherein the first and second word lines are from the same block.

11. The method of claim 1, further comprising:

reading one or more additional pages of data from a corresponding word lines of the array; and

storing the one or more additional pages of data in latches for each of the bit lines of the array, wherein the one or more arithmetical/logical operations further involve the data of the one or more additional pages of data.

12. The method of claim 1, subsequently further comprising

reading a third page of data from the array;

storing the third page of data in the first of the latches for each of the bit lines of the array;

reading a fourth page of data from the array;

storing the fourth page of data in the second of the latches for each of the bit lines of the array;

subsequently performing within said sets of latches the one or more arithmetical/logical operations upon the contents of the first and second latches;

subsequently writing the result of the one or more arithmetical/logical operations from the sets of latches along a word line the array.

13. The method of claim 12, wherein the first, second, third and fourth pages of data are all read from different word lines of the array.

14. The method of claim 1, wherein the one or more arithmetical/logical operations include floating point operations.

15. The method of claim 1, further comprising:

prior to reading the first and second pages of data, writing a plurality of data sets selected by a host in the array, where the data sets are written oriented along the bit lines with corresponding data elements arranged to lie along the same word lines, the first and second pages of data being read from said data sets.

16. The method of claim 15, where the array is formed of multiple blocks of NAND strings formed along the bit lines, and wherein the first and second pages of are read respectively from first and second blocks, the second page of data begin read from a word line of the second block corresponding to a word line of the first block from which the first page of data was written.

17. The method of claim 16, wherein the second block holds an updated version of data sets in the first block.

18. The method of claim 16, wherein the second block holds data sets in the first block, but which are aligned along different bit lines than in the first block.