Semiconductor device

• US 8,634,266 B2
• Filed: 09/13/2012
• Issued: 01/21/2014
• Est. Priority Date: 01/30/2004
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi
• Primary Examiner(s): Le, Vu
• Application Number:
  US13/613,428
• Publication Number:
  US 20130016579A1
• Time in Patent Office: 495 Days
• Field of Search: 365/226, 365/227, 365/229, 713/324, 713/103, 235/492
• US Class Current: 365/226
• CPC Class Codes: G11C 5/142 Contactless power supplies, e.g. RF, induction, or IR
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

A semiconductor device capable of stabilizing power supply by suppressing power consumption as much as possible. The semiconductor device of the invention includes a central processing unit having a plurality of units and a control circuit, and an antenna. The control circuit includes a means for outputting, based on a power supply signal including data on power supply from an antenna (through an antenna) or a load signal obtained by an event signal supplied from each of the units, one or more of a first control signal for stopping power supply to one or more of the units, a second control signal for varying a power supply potential supplied to one or more of the units, and a third control signal for stopping supplying a clock signal to one or more of the units.

Claims

1. A semiconductor device comprising:

a CPU comprising an unit;

a power source circuit configured to supply a first potential and a second potential;

a control circuit operationally connected to the CPU;

a memory block comprising a memory cell array;

a first switch configured to selectively supply the unit with one of the first potential and the second potential in accordance with a first control signal from the control circuit; and

a second switch configured to selectively supply the memory cell array with one of the first potential and the second potential in accordance with a second control signal from the control circuit.

2. The semiconductor device according to claim 1, further comprising a third switch,

wherein the memory block further comprises a decoder, and

wherein the third switch is configured to selectively supply the decoder with one of the first potential and the second potential in accordance with a third control signal from the control circuit.

3. The semiconductor device according to claim 1, further comprising a dedicated circuit configured to output an operation signal to the control circuit.

4. The semiconductor device according to claim 1, wherein the control circuit is configured to output the first control signal in accordance with an event signal supplied from the unit.

5. The semiconductor device according to claim 1, wherein the control circuit is configured to output the second control signal and to set the memory block to a normal mode or a standby mode.

6. The semiconductor device according to claim 1, wherein the unit is one of a bus interface, a data cache, an instruction decoder, a reservation station, an instruction cache, a pipeline register including an arithmetic logical unit, and a general purpose register.

7. A semiconductor device comprising:

a first unit;

a second unit;

a power source circuit configured to supply a first potential and a second potential;

a control circuit;

a memory block comprising a memory cell array;

a first switch configured to selectively supply the first unit with one of the first potential and the second potential in accordance with a first control signal from the control circuit;

a second switch configured to selectively supply the second unit with one of the first potential and the second potential in accordance with a second control signal from the control circuit; and

a third switch configured to selectively supply the memory block with one of the first potential and the second potential in accordance with a third control signal from the control circuit.

8. The semiconductor device according to claim 7, further comprising a CPU operationally connected to the control circuit,

wherein the CPU comprises the first unit and the second unit.

9. The semiconductor device according to claim 7, further comprising a fourth switch,

wherein the memory block further comprises a decoder, and

wherein the fourth switch is configured to selectively supply the decoder with one of the first potential and the second potential in accordance with a fourth control signal from the control circuit.

10. The semiconductor device according to claim 7, further comprising a dedicated circuit configured to output an operation signal to the control circuit.

11. The semiconductor device according to claim 7, wherein the control circuit is configured to output the first control signal in accordance with an event signal supplied from the first unit.

12. The semiconductor device according to claim 7, wherein the control circuit is configured to output the third control signal and to set the memory block to a normal mode or a standby mode.

13. The semiconductor device according to claim 7, wherein each of the first unit and the second unit is one of a bus interface, a data cache, an instruction decoder, a reservation station, an instruction cache, a pipeline register including an arithmetic logical unit, and a general purpose register.

14. A semiconductor device comprising:

an unit;

a power source circuit configured to supply a first potential and a second potential;

a control circuit;

a first memory block comprising a first memory cell array and a first row decoder;

a second memory block comprising a second memory cell array and a second row decoder;

a column decoder operationally connected to the first memory block and the second memory block;

a first switch configured to selectively supply the unit with one of the first potential and the second potential in accordance with a first control signal from the control circuit;

a second switch configured to selectively supply the first memory block with one of the first potential and the second potential in accordance with a second control signal from the control circuit; and

a third switch configured to selectively supply the second memory block with one of the first potential and the second potential in accordance with a third control signal from the control circuit.

15. The semiconductor device according to claim 14, further comprising a CPU operationally connected to the control circuit,

wherein the CPU comprises the unit.

16. The semiconductor device according to claim 14, further comprising a fourth switch and a fifth switch,

wherein the fourth switch is configured to selectively supply the first row decoder with one of the first potential and the second potential in accordance with a fourth control signal from the control circuit, and

wherein the fifth switch is configured to selectively supply the second row decoder with one of the first potential and the second potential in accordance with a fifth control signal from the control circuit.

17. The semiconductor device according to claim 14, further comprising a dedicated circuit configured to output an operation signal to the control circuit.

18. The semiconductor device according to claim 14, wherein the control circuit is configured to output the first control signal in accordance with an event signal supplied from the unit.

19. The semiconductor device according to claim 14, wherein the control circuit is configured to output the second control signal and to set the first memory block to a normal mode or a standby mode.

20. The semiconductor device according to claim 14, wherein the unit is one of a bus interface, a data cache, an instruction decoder, a reservation station, an instruction cache, a pipeline register including an arithmetic logical unit, and a general purpose register.