Multiphase receiver with equalization circuitry
First Claim
1. An integrated circuit having a pin adapted for electrical communication with a signaling path to receive an electrical input signal therefrom, comprising:
- a first circuit operable to receive bits associated with a first data cycle of the electrical input signal and operable to produce a decision regarding logic state of the bits associated with the first data cycle;
a second circuit operable to receive bits associated with a second cycle of the electrical input signal and operable to produce a decision regarding logic state of the bits associated with the second data cycle; and
an equalizing circuit operable to compensate for intersymbol interference affecting the second circuit dependent on an output of the first circuit and operable to compensate for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal.
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Accused Products
Abstract
An integrated circuit device includes a first circuit to receive bits associated with a first data cycle of an electrical input signal, operable to produce a decision regarding logic state of the bits associated with the first data cycle, and a second circuit to receive bits associated with a second cycle of the electrical input signal, to produce a decision regarding logic state of the bits associated with the second data cycle. An equalizing circuit compensates for intersymbol interference affecting the second circuit dependent on an output of the first circuit and compensates for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal.
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Citations
26 Claims
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1. An integrated circuit having a pin adapted for electrical communication with a signaling path to receive an electrical input signal therefrom, comprising:
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a first circuit operable to receive bits associated with a first data cycle of the electrical input signal and operable to produce a decision regarding logic state of the bits associated with the first data cycle; a second circuit operable to receive bits associated with a second cycle of the electrical input signal and operable to produce a decision regarding logic state of the bits associated with the second data cycle; and an equalizing circuit operable to compensate for intersymbol interference affecting the second circuit dependent on an output of the first circuit and operable to compensate for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. An integrated circuit having pins adapted for electrical communication with two signaling paths to receive a differential input signal therefrom, comprising:
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a first circuit operable to receive bits associated with a first data cycle of the differential input signal, the first circuit operable to produce an output having a first logic state when a first one of the two signaling paths has a voltage greater than a second one of the two signaling paths, and having a second logic state when the second one of the two signaling paths has a voltage greater than the first one of the signaling paths; a second circuit operable to receive bits associated with a second cycle of the differential input signal, the second circuit operable to produce an output having a first logic state when a first one of the two signaling paths has a voltage greater than a second one of the two signaling paths, and having a second logic state when the second one of the two signaling paths has a voltage greater than the first one of the signaling paths; and an equalizing circuit operable to compensate for intersymbol interference affecting the second circuit dependent on an output of the first circuit and operable to compensate for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to receive bits of the differential input signal. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. An integrated circuit having pins adapted for electrical communication with corresponding signaling paths to receive an electrical differential signal therefrom for each of multiple signaling lanes, the integrated circuit comprising for each of the multiple signaling lanes:
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a first circuit operable to receive bits associated with a first data cycle of the electrical differential signal, the first circuit operable to produce an output having a first logic state when a first one of the two signaling paths has a voltage greater than a second one of the two signaling paths, and having a second logic state when the second one of the two signaling paths has a voltage greater than the first one of the signaling paths; a second circuit operable to receive bits associated with a second cycle of the electrical differential signal, the second circuit operable to produce an output having a first logic state when a first one of the two signaling paths has a voltage greater than a second one of the two signaling paths, and having a second logic state when the second one of the two signaling paths has a voltage greater than the first one of the signaling paths; and an equalizing circuit operable to compensate for intersymbol interference affecting the second circuit dependent on an output of the first circuit and operable to compensate for intersymbol interference affecting the first circuit dependent on an output of the second circuit. - View Dependent Claims (26)
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Specification