Multiphase receiver with equalization circuitry

• US 8,634,452 B2
• Filed: 06/07/2012
• Issued: 01/21/2014
• Est. Priority Date: 10/19/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared L., Garlepp, Bruno W., Chau, Pak S., Donnelly, Kevin S., Horowitz, Mark A., Sidiropoulos, Stefanos, Garrett, Billy W. Jr., Werner, Carl W.
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US13/491,508
• Publication Number:
  US 20130010855A1
• Time in Patent Office: 593 Days
• Field of Search: 375224-330, 327/336
• US Class Current: 375/227
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling
• CPC Class Codes: H04L 25/0296 Arrangements to ensure DC-balance
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/08 : Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/4902 : Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 25/4917 : using multilevel codes
• CPC Class Codes: H04L 7/0331 : with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/0332 : with an integrator-detector

Abstract

An integrated circuit device includes a first circuit to receive bits associated with a first data cycle of an electrical input signal, operable to produce a decision regarding logic state of the bits associated with the first data cycle, and a second circuit to receive bits associated with a second cycle of the electrical input signal, to produce a decision regarding logic state of the bits associated with the second data cycle. An equalizing circuit compensates for intersymbol interference affecting the second circuit dependent on an output of the first circuit and compensates for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal.

Claims

1. An integrated circuit having a pin adapted for electrical communication with a signaling path to receive an electrical input signal therefrom, comprising:

a first circuit operable to receive bits associated with a first data cycle of the electrical input signal and operable to produce a decision regarding logic state of the bits associated with the first data cycle;

a second circuit operable to receive bits associated with a second cycle of the electrical input signal and operable to produce a decision regarding logic state of the bits associated with the second data cycle; and

an equalizing circuit operable to compensate for intersymbol interference affecting the second circuit dependent on an output of the first circuit and operable to compensate for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal.

2. The integrated circuit of claim 1, where the equalizing circuit is operable to compensate for intersymbol interference affecting the first circuit dependent on the output of the second circuit.

3. The integrated circuit of claim 2, where the equalizing circuit further comprises a first adjustment circuit operable to adjust a voltage used by the equalizing circuit to compensate for intersymbol interference affecting the second circuit dependent on the output of the first circuit and a second adjustment circuit operable to adjust a voltage used by the equalizing circuit to compensate for intersymbol interference affecting the first circuit dependent on the output of the second circuit.

4. The integrated circuit of claim 2, where the integrated circuit further comprises a preamplifier circuit in electrical communication with the pin and operable to receive the electrical input signal therefrom, the integrated circuit operable to cause each of the first and second circuits to sample the electrical input signal on reciprocal edges of a clock signal.

5. The integrated circuit of claim 4, where:

the preamplifier circuit is operable to provide a differential output signal to each of the first and second circuits dependent on the electrical input signal; and

the equalizing circuit is operable to compensate for the intersymbol interference by adjusting a first one of two components of the differential output signal dependent on an immediately prior bit of information carried by the differential output signal, and by adjusting the second one of two components of the differential output signal dependent the immediately prior bit of information carried by the differential output signal.

6. The integrated circuit of claim 5, where the equalizing circuit is operable to compensate for the intersymbol interference by adjusting the first one of two components of the differential output signal dependent on voltage carried by the second one of the two components for the immediately prior bit of information carried by the differential output signal, and by adjusting the second one of two components of the differential output signal dependent on voltage carried by the first one of the two components for the immediately prior bit of information carried by the differential output signal.

7. The integrated circuit of claim 4, where each of the first and second circuits includes at least one integrating receiver.

8. The integrated circuit of claim 1, where:

each of the first and second circuits comprises a sense amplifier and a latch, where each sense amplifier is operable to receive a present signal representing a present bit and to produce a decision regarding the present bit and where the corresponding latch is operable to output a logic level dependent on the respective decision; and

the equalization circuit is operable to precharge of each sense amplifier in dependence on the immediately prior bit of information carried by the electrical input signal.

9. The integrated circuit of claim 1, further comprising a circuit operable to adjust a voltage used by the equalizing circuit to compensate for intersymbol interference affecting the second circuit dependent on the output of the first circuit and a voltage used by the equalizing circuit to compensate for intersymbol interference affecting the first circuit dependent on the output of the circuit other than the first circuit.

10. The integrated circuit of claim 1, where the equalizing circuit further comprises a register operable to receive and store a value representing the voltage used by the equalizing circuit to compensate for intersymbol interference affecting at least one of the first circuit or the second circuit, and a digital-to-analog converter operable to receive the value from the register and to responsively generate an analog voltage.

11. The integrated circuit of claim 10, where the electrical input signal is a differential input signal received by corresponding pins of the integrated circuit, and where the equalizing circuit is operable to compensate for the intersymbol interference by adjusting voltage provided by each component of the differential signal dependent on relative voltage of the other component associated with an immediately prior bit of information carried by the differential input signal.

12. The integrated circuit of claim 10, where the integrated circuit has plural instances of the pin adapted for electrical communication with each of multiple data links to receive respective input signals therefrom, and where the integrated circuit further comprises an instance of said first circuit, said second circuit and said equalizing circuit for each of the multiple data links.

13. The integrated circuit of claim 1, further comprising a circuit adapted to compensate for offset voltage associated with each of the first circuit and the second circuit.

14. An integrated circuit having pins adapted for electrical communication with two signaling paths to receive a differential input signal therefrom, comprising:

a first circuit operable to receive bits associated with a first data cycle of the differential input signal, the first circuit operable to produce an output having a first logic state when a first one of the two signaling paths has a voltage greater than a second one of the two signaling paths, and having a second logic state when the second one of the two signaling paths has a voltage greater than the first one of the signaling paths;

a second circuit operable to receive bits associated with a second cycle of the differential input signal, the second circuit operable to produce an output having a first logic state when a first one of the two signaling paths has a voltage greater than a second one of the two signaling paths, and having a second logic state when the second one of the two signaling paths has a voltage greater than the first one of the signaling paths; and

an equalizing circuit operable to compensate for intersymbol interference affecting the second circuit dependent on an output of the first circuit and operable to compensate for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to receive bits of the differential input signal.

15. The integrated circuit of claim 14, where the integrated circuit further comprises a preamplifier circuit in electrical communication with the pins in manner operable to receive the differential input signal therefrom, the integrated circuit operable to cause each of the first and second circuits to sample the differential input signal on different edges of a clock signal.

16. The integrated circuit of claim 15, where:

the preamplifier circuit is operable to provide a differential output signal to each of the first and second circuits dependent on the differential input signal; and

the equalizing circuit is operable to compensate for the intersymbol interference by adjusting a first one of two components of the differential output signal dependent on a prior state of the second of the two components for an immediately prior bit of information carried by the differential input signal.

17. The integrated circuit of claim 16, where:

each of the first and second circuits comprises a sense amplifier and a latch, where each sense amplifier is operable to receive a present differential signal representing a present bit and to produce a decision regarding a logic level of the present bit and the corresponding latch is operable to output a logic level dependent on the decision; and

the equalization circuit is operable to precharge an input of each sense amplifier in dependence on the immediately prior bit of information carried by the differential input signal.

18. The integrated circuit of claim 17, where each of the first and second circuits includes at least one integrating receiver.

19. The integrated circuit of claim 14, further comprising a circuit operable to adjust a voltage used by the equalizing circuit to compensate for intersymbol interference affecting the second circuit dependent on the output of the first circuit and a voltage used by the equalizing circuit to compensate for intersymbol interference affecting the first circuit dependent on the output of the circuit other than the first circuit.

20. The integrated circuit of claim 19, where the equalizing circuit further comprises a register to receive and store a value representing the voltage used by the equalizing circuit to compensate for intersymbol interference affecting at least one of the first circuit or the second circuit, and a digital-to-analog converter operable to receive the value from the register and to responsively generate an analog voltage.

21. The integrated circuit of claim 14, where the circuit other than the first circuit is the second circuit, and where the equalizing circuit further comprises a first circuit operable to adjust a voltage used by the equalizing circuit to compensate for intersymbol interference affecting the second circuit dependent on the output of the first circuit and a second circuit operable to adjust a voltage used by the equalizing circuit to compensate for intersymbol interference affecting the first circuit dependent on the output of the second circuit.

22. The integrated circuit of claim 21, where the integrated circuit has plural instances of the pins adapted for electrical communication with differential component paths for each of multiple data links to receive respective differential input signals therefrom, and where the integrated circuit further comprises an instance of said first circuit, said second circuit and said equalizing circuit for each of the multiple data links.

23. The integrated circuit of claim 22, embodied as a dynamic random access memory (DRAM) integrated circuit.

24. The integrated circuit of claim 22, further comprising means for compensating for offset voltage associated with the first circuit and for compensating for offset voltage associated with the second circuit.

25. An integrated circuit having pins adapted for electrical communication with corresponding signaling paths to receive an electrical differential signal therefrom for each of multiple signaling lanes, the integrated circuit comprising for each of the multiple signaling lanes:

a first circuit operable to receive bits associated with a first data cycle of the electrical differential signal, the first circuit operable to produce an output having a first logic state when a first one of the two signaling paths has a voltage greater than a second one of the two signaling paths, and having a second logic state when the second one of the two signaling paths has a voltage greater than the first one of the signaling paths;

a second circuit operable to receive bits associated with a second cycle of the electrical differential signal, the second circuit operable to produce an output having a first logic state when a first one of the two signaling paths has a voltage greater than a second one of the two signaling paths, and having a second logic state when the second one of the two signaling paths has a voltage greater than the first one of the signaling paths; and

an equalizing circuit operable to compensate for intersymbol interference affecting the second circuit dependent on an output of the first circuit and operable to compensate for intersymbol interference affecting the first circuit dependent on an output of the second circuit.

26. The integrated circuit of claim 25, where the first and second circuits for at least one of the signaling lanes each comprise a sense amplifier and where the equalizing circuit is operable to compensate for intersymbol interference by adjusting a precharge voltage of each of the sense amplifiers dependent on an immediately previous bit of information carried by the differential input signal for the respective at least one of the signaling lanes.