Method, system and apparatus for handling events for partitions in a socket with sub-socket partitioning
First Claim
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1. A method comprising:
- defining a plurality of partitions, within a processor socket including, configured on a die, a plurality of cores, a memory controller, a first level ring interconnect to interconnect the plurality of cores with a distributed last level cache (LLC), a fabric interface, a home agent coupled to the memory controller, and a second level interconnect to interconnect the home agent and the fabric interface for sub-socket partitioning;
receiving an event, wherein the event is a reset, interrupt, error, or reliability, availability, and serviceability (RAS) condition, wherein the reset is a partition specific reset of a specific partition; and
isolating the event to a partition within the processor socket.
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Abstract
In one aspect, the issues of events that may impact one or more partitions of sub-socket partitioning in one or more sockets can be handled. Specifically, events for partitions can be handled in a socket with sub-socket partitioning, wherein the events may include reset, interrupts, errors and reliability, availability, and serviceability (RAS) management.
23 Citations
13 Claims
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1. A method comprising:
- defining a plurality of partitions, within a processor socket including, configured on a die, a plurality of cores, a memory controller, a first level ring interconnect to interconnect the plurality of cores with a distributed last level cache (LLC), a fabric interface, a home agent coupled to the memory controller, and a second level interconnect to interconnect the home agent and the fabric interface for sub-socket partitioning;
receiving an event, wherein the event is a reset, interrupt, error, or reliability, availability, and serviceability (RAS) condition, wherein the reset is a partition specific reset of a specific partition; and
isolating the event to a partition within the processor socket. - View Dependent Claims (2, 3, 4, 5, 6)
- defining a plurality of partitions, within a processor socket including, configured on a die, a plurality of cores, a memory controller, a first level ring interconnect to interconnect the plurality of cores with a distributed last level cache (LLC), a fabric interface, a home agent coupled to the memory controller, and a second level interconnect to interconnect the home agent and the fabric interface for sub-socket partitioning;
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7. A system comprising:
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a processor configured on a die within a socket and having a plurality of cores, a first level ring interconnect to couple the plurality of cores to a distributed last level cache (LLC), a fabric interface, a home agent coupled to a memory controller, and a second level interconnect to interconnect the home agent and the fabric interface; a dynamic random access memory, coupled to the socket, to receive requests from the processor; the processor to support sub-socket partitioning of the processor to utilize at least a first operating system and a second operating system within a first partition and a second partition; the processor to receive an event and to isolate the event to either the first partition or the second partition within the socket, wherein the event is a reset, interrupt, error, or reliability, availability, and serviceability (RAS) condition, wherein the reset is a partition specific reset; and a system service processor (SSP) coupled to the processor. - View Dependent Claims (8, 9, 10)
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11. A processor comprising:
- a processor socket including, on a die;
a plurality of processor cores, a memory controller, a first level ring interconnect to interconnect the plurality of processor cores with a distributed last level cache (LLC), a fabric interface, a home agent coupled to a memory controller, and a second level interconnect to interconnect the home agent and the fabric interface, wherein the plurality of processor cores support sub-socket partitioning that allows a plurality of partitions within the processor socket, each of the partitions to execute a different operating system;
the processor to receive an event comprising a reset, interrupt, error, or reliability, availability, and serviceability (RAS) condition, wherein the reset is a partition specific reset of a specific partition; and
wherein an interrupt logic is coupled to the processor, to facilitate handling of the interrupt by isolating the interrupt to a partition of the plurality of partitions based at least in part on information in a mapping table of the interrupt logic. - View Dependent Claims (12, 13)
- a processor socket including, on a die;
Specification