Data processing apparatus, control device and data storage device

• US 8,635,511 B2
• Filed: 08/08/2011
• Issued: 01/21/2014
• Est. Priority Date: 08/11/2010
• Status: Active Grant

• Current Assignee: University of Tokyo
• Original Assignee: University of Tokyo
• Inventors: Takeuchi, Ken, Fukuda, Mayumi
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US13/205,239
• Publication Number:
  US 20120072801A1
• Time in Patent Office: 897 Days
• Field of Search: 714/763, 714/759, 714/746, 714/785, 714/766, 714/755, 714/758, 714/720
• US Class Current: 714/763
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

When write data D is high rewritten data, a PC 10 controls a DRAM 24 to store the write data D (steps S100 and S110). When the write data D is not the high rewritten data, the PC 10 outputs an RRAM write request signal and the write data D to an SSD (step S100 and S120). A memory controller of the SSD input the RRAM write request signal controls the RRAM and an SRAM to store the write data D in the RRAM or the SRAM. This treatment enables data stored in the DRAM to be rewritten frequently. Therefore, the decrease of number of times of refresh operation of the DRAM and the decrease of power consumption are accomplished.

Claims

1. A data processing apparatus configured to process data, the data processing apparatus comprising:

a first memory configured to be a dynamic random access memory;

a second memory configured to be a nonvolatile random access memory storing data; and

a control processing unit configured to control the first memory to store write data to write in the first memory when the write data is high rewritten data having a high number of rewrite times and to control the second memory to store the write data in the second memory when the write data is not the high rewritten data.

2. The data processing apparatus in accordance with claim 1, wherein the control processing unit comprises:

a first control unit configured to control the first memory to store the write data in the first memory when the write data is the high rewritten data and to output the write data and a second memory write request signal requesting to write data in the second memory when the write data is not the high rewritten data; and

a second control unit configured to control the second memory to store the input data when the second memory write request signal is input.

3. The data processing apparatus in accordance with claim 2, wherein the first control unit of the control processing unit is configured to output the second memory write request signal, the write data and information of logical address when the write data is not the high rewritten data, and

the second control unit of the control processing unit comprises:

a volatile memory unit configured to be a volatile random access memory different from dynamic random access memory;

a conversion table memory unit configured to generate and store an address conversion table when the second memory write request signal is input, the address conversion table being showing relation between the information of the logical address and information of a physical address in the second memory in converting the input information of the logical address into information of the physical address to rewrite data in an area of a storage area capable of storing data in the second memory, the area of the storage area capable of storing data having comparatively less number of the rewrite times; and

a memory control unit configured to control the second memory to read out the stored address conversion table, convert the input information of the logical address into the information of the physical address using the read address conversion table, and control the second memory to store the write data in an area of the second memory equivalent to the converted information of the physical address when the second memory write request signal is input and the input write data has size of equal to or more than predefined size, and to control the volatile memory unit to store the write data in an area of the volatile memory unit equivalent to the input logical address even as the second memory write request signal is input when the input write data has size of less than predefined size.

4. The data processing apparatus in accordance with claim 3, wherein the second control unit of the control processing unit further comprises a timer unit measuring the length of elapsed time since the write data having size of less than the predefined size is input, and

the memory control unit reads out data stored in the volatile memory unit and controls the second memory to store the read data when the input data from the first control unit has size of equal to or more than the predefined size before the length of elapsed time exceeds the predefined time.

5. The data processing apparatus in accordance with claim 2, the data processing apparatus further comprising:

a nonvolatile storage device configured to be as a nonvolatile type storage device; and

a fourth memory configured to be as nonvolatile random access memory,

wherein the first control unit of the control processing unit outputs storage device write request signal and the write data to the second control unit when writing data in the nonvolatile storage device is requested, outputs storage device readout request signal to the second control unit when reading out data from the nonvolatile storage device is requested, and outputs second memory readout request signal to the second control when reading out data from the second memory is requested,

the second control unit of the control processing unit comprises;

a first encoding processing unit configured to control the nonvolatile storage device to store the input write data in the nonvolatile storage device when the storage device write request signal is input and the input write data is not high frequent access data read and written frequently, and to encode the input write data into first error correction code and control the fourth memory to store the encoded data when the storage device write request signal is input and the input write data is the high frequent access data;

a second encoding processing unit configured to encode the input write data into a second error correction code correcting less errors than the first error correction code and control the second memory to store the encoded data when the second memory write request signal is input;

a first decoding processing unit configured to control the nonvolatile storage device to read out data from the nonvolatile storage device when the storage readout request signal is input and output data to be output is not the high frequent access data, and to control the fourth memory to read out data from the fourth memory, perform error correction and decoding the read data as the first error correction code, and output the decoded data to the first control unit when the storage readout request signal is input and the output data is the high frequent access data; and

a second decoding processing unit configured to control the second memory to read out data from the second memory, perform error correction and decoding the read data as the second error correction code, and output the decoded data to the first control unit when the second memory readout request signal is input.

6. The data processing apparatus in accordance with claim 5, wherein the first error correction code is Bose-Chaudhuri-Hocquenghem (BCH) code having first size of codeword obtained by adding parity bit to the write data, and

the second error correction code is BCH code having second size of codeword, the second size being shorter than the first size.

7. The data processing apparatus in accordance with claim 5, wherein the second memory and the fourth memory are equipped on the same semiconductor chip.

8. The data processing apparatus in accordance with claim 5, wherein the first memory and the control processing unit are equipped on first semiconductor chip,

the second memory and the fourth memory are equipped on the second semiconductor chip different from the first semiconductor chip,

the nonvolatile storage device is a flash memory equipped on third semiconductor chip different from the first semiconductor chip and the second semiconductor chip,

three chips of the first semiconductor chip, the second semiconductor chip and the third semiconductor chip are stacked, and

the three chips are electrically connected with each other by conductor metal electrodes filled in a plurality of via holes formed in each chips.

9. The data processing apparatus in accordance with claim 5, wherein the nonvolatile device is a hard disk drive.

10. The data processing apparatus in accordance with claim 2, wherein the first control unit of the control processing unit reads out data stored in the first memory, outputs the second memory write request signal, outputs the read data as write data to the second control unit, then cuts off power supply from external power supply to the first memory, the second memory and the second control unit when stop of the data processing apparatus is requested.

11. The data processing apparatus in accordance with claim 10, the data processing apparatus further comprising a third memory configured to be a volatile random access memory different from a dynamic random access memory,

wherein the first control unit of the control processing unit reads out data stored in the first memory and the third memory, outputs the second memory write request signal, outputs the read data as write data to the second control unit, then cuts off power supply from external power supply to the first memory, the second memory, the third memory and the second control unit when the stop of the data processing apparatus is requested.

12. The data processing apparatus in accordance with claim 2, the data processing apparatus further comprising a third memory configured to be a volatile random access memory different from a dynamic random access memory,

wherein the first control unit of the control processing unit reads out data stored in the first memory and data stored in the third memory, outputs the second memory write request signal, outputs the read data as write data to the second control unit, then cuts off power supply from external power supply to the first memory, the second memory, the third memory and the second control unit when the stop of the data processing apparatus is requested.

13. The data processing apparatus in accordance with claim 2, wherein the control processing unit controls the first memory and the second memory to read out data stored in the first memory and then store the read data in the second memory, and cuts off power supply from external power supply to the first memory and the second memory after finishing storing data in the second memory when the stop of the data processing apparatus is requested.

14. The data processing apparatus in accordance with claim 13, the data processing apparatus further comprising a third memory configured to be a volatile random access memory different from a dynamic random access memory,

wherein the control processing unit controls the first memory, the second memory and the third memory to read out data stored in the first memory and data stored in the third memory and then store the read data in the second memory, and cuts off power supply from external power supply to the first memory, the second memory and the third memory after finishing storing data in the third memory when the stop of the data processing apparatus is requested.

15. The data processing apparatus in accordance with claim 4, wherein the volatile random access memory is any one of a dynamic random access memory and a static random access memory.

16. The data processing apparatus in accordance with claim 1, wherein the nonvolatile random access memory is any one of a resistance random access memory, a ferroelectric random access memory, a magnetoresistive random access memory, and a phase change memory.

17. A data processing apparatus configured to process data, the data processing apparatus comprising:

a first memory configured to be a volatile random access memory;

a second memory configured to be a nonvolatile random access memory; and

a control processing unit configured to control the first memory and the second memory to read out data stored in the first memory and then store the read data in the second memory, and cuts off power supply from external power supply to the first memory and the second memory after finishing storing data in the second memory when stop of the data processing apparatus is requested.

18. The data processing apparatus in accordance with claim 17, wherein the control processing unit comprises:

a second memory control unit configured to control the second memory to store the input data and then output a second memory write stop signal when a second memory write request signal requesting writing data in the second memory is input; and

a first memory control unit configured to read out data stored in the first memory and output the read data and the second memory write request signal to the second memory control unit when the stop of the data processing apparatus is requested, and to cut off power supply from external power supply to the first memory, the second memory and the second memory control unit when the second memory write stop signal is input.

19. The data processing apparatus in accordance with claim 17, wherein the volatile random access memory is any one of a dynamic random access memory and a static random access memory.

20. The data processing apparatus in accordance with claim 17, wherein the nonvolatile random access memory is any one of a resistance random access memory, a ferroelectric random access memory, a magnetoresistive random access memory, and a phase change memory.

21. A control device configured to control a nonvolatile memory configured to be as a nonvolatile random access memory to store write data input from a host sequentially in an area equivalent to information of logical address input from the host device, the control device comprising:

a volatile memory unit configured to be a volatile random access memory;

a conversion table memory unit configured to generate and store an address conversion table when write request signal requesting data input from the host device in the nonvolatile memory is input, the address conversion table being showing relation between the information of the logical address and information of a physical address in the nonvolatile memory in converting the input information of the logical address into information of the physical address to rewrite data in an area of a storage area capable of storing data in the nonvolatile memory, the area of the storage area capable of storing data having comparatively less number of the rewrite times; and

a memory control unit configured to convert the input information of the logical address into the information of the physical address using the stored address conversion table and control the nonvolatile memory to store the write data in an area of the nonvolatile memory equivalent to the converted information of the physical address when the write request signal is input and the input write data has size of equal to or more than predefined size, and to control the volatile memory unit to store the write data in an area of the volatile memory unit equivalent to the input logical address even as the write request signal is input when the input write data has size of less than predefined size.

22. The control device in accordance with claim 21, the control device further comprising a timer unit measuring the length of elapsed time since the write data having size of less than the predefined size is input,

wherein the memory control unit reads out data stored in the volatile memory unit and controls the nonvolatile memory to store the read data when the sequent input write data has size of equal to or more than the predefined size before the length of elapsed time exceeds the predefined time.

23. The control device in accordance with claim 21, wherein the volatile random access memory is a static random access memory.

24. A data storage device storing data, the data storage device comprising:

the control device in accordance with claim 21;

a first storage device configured to be as a nonvolatile storage device; and

a second storage device configured to be as the volatile memory.

25. The data storage device in accordance with claim 24, wherein the first storage device is any one of flash memory and a hard disk drive, and

the second storage device is any one of a resistance random access memory, a ferroelectric random access memory, a magnetoresistive random access memory, and a phase change memory.

26. A control device transferring data between a host device, a nonvolatile storage device configured to be as a nonvolatile type storage device, a first nonvolatile memory configured to be as a nonvolatile random access memory, and a second nonvolatile memory configured to be as the nonvolatile random access memory, the control device comprising:

a first encoding processing unit configured to control the nonvolatile storage device to store the input write data from the host device when the storage device write request signal requesting writing data in the nonvolatile storage device is input from the host device and the input write data from the host device is not high frequent access data read and written frequently, and to encode the input write data into first error correction code and control the first nonvolatile memory to store the encoded data when the storage device write request signal is input from the host device and the input write data is the high frequent access data;

a second encoding processing unit configured to encode the input write data into a second error correction code correcting less errors than the first error correction code and control the second nonvolatile memory to store the encoded data when the memory write request signal requesting writing data in the second nonvolatile memory is input from the host device;

a first decoding processing unit configured to control the nonvolatile storage device to read out data from the nonvolatile storage device when the storage readout request signal requesting reading out data in the nonvolatile storage device is input from the host device and output data to be output is not the high frequent access data, and to control the first nonvolatile memory to read out data from the first nonvolatile memory, perform error correction and decoding the read data as the first error correction code, and output the decoded data to the host device when the storage readout request signal is input from the host device and the output data is the high frequent access data; and

a second decoding processing unit configured to control the second nonvolatile memory to read out data from the second nonvolatile memory, perform error correction and decoding the read data as the second error correction code, and output the decoded data to the host device when memory readout request signal requesting reading out data from the second nonvolatile memory is input from the host device.

27. The control device in accordance with claim 26, wherein the first error correction code is Bose-Chaudhuri-Hocquenghem (BCH) code having first size of codeword obtained by adding parity bit to the write data, and

the second error correction code is BCH code having second size of codeword, the second size being shorter than the first size.

28. A data storage device storing data, the data storage device comprising:

the control device in accordance with claim 26;

a first storage device configured to be as a nonvolatile storage device; and

a second storage device comprising the first nonvolatile memory and the second nonvolatile memory.

29. The data storage device in accordance with claim 28, wherein the first storage device is any one of flash memory and a hard disk drive, and

the first nonvolatile memory and the second nonvolatile memory of the second storage device are any one of a resistance random access memory, a ferroelectric random access memory, a magnetoresistive random access memory, and a phase change memory.

30. A data processing apparatus processing data, the data processing apparatus comprising:

a nonvolatile memory configured to be as a nonvolatile random access memory and store data;

an information output unit configured to output reliability information including information of reliability of the nonvolatile memory; and

a control processing unit configured to execute a predefined process using the output reliability information.

31. The data processing apparatus in accordance with claim 30, wherein the reliability information includes any one of a first information, a second information, a third information, a fourth information and a fifth information, the first information being number of error bits of data stored in the nonvolatile memory, the second information being maximum value of number of rewritable times for the nonvolatile memory before predefined period passes, the third information being total of rewrite times after beginning of use of the data processing apparatus, the fourth information being number of rewritable bits in the nonvolatile memory before the predefined period passes, the fifth information being total of rewrite bits in the nonvolatile memory after the beginning of the use of the data processing apparatus.