Circuitry having programmable power rails, architectures, apparatuses, and systems including the same, and methods and algorithms for programming and/or configuring power rails in an integrated circuit

• US 8,635,572 B1
• Filed: 04/09/2013
• Issued: 01/21/2014
• Est. Priority Date: 05/25/2010
• Status: Expired due to Fees

• Current Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Jin, Jianwen, Ye, Eugene
• Primary Examiner(s): DOAN, NGHIA M
• Application Number:
  US13/859,220
• Time in Patent Office: 287 Days
• Field of Search: 716118-120, 716126-130, 716132-133, 716/135, 716/139, 326/30, 326/33, 326/41, 326/47, 326/63, 326/80
• US Class Current: 716/120
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

Circuits, architectures, a system and methods for providing multiple power rails to a plurality of standard cells in a region of an integrated circuit. The circuitry generally includes a plurality of cells configured for connection to a first or second power rail, the first power rail providing a first voltage to at least one of the plurality of cells, and the second power rail providing a second voltage (which may be independent from the first voltage) to remaining cells in the plurality of cells. The method generally includes routing, in an IC layout, a first power rail providing a first voltage and a second power rail providing a second voltage, placing the plurality of cells, and selectively connecting first and second subsets of the plurality of cells to the first and second power rails, respectively. The present invention further advantageously minimizes regional layout design considerations and time delays.

Claims

1. A circuit comprising:

a plurality of cells in a first region of said circuit, each of said plurality of cells being configured for connection to any one of a plurality of power rails, wherein;

a first subset of cells of the plurality of cells has first and second power pins;

the first power pin is configured for connection to a first power rail of said plurality of power rails, and the second power pin is configured for connection to a second power rail of said plurality of power rails;

the first power rail is coupled to the first subset of cells through the first power pin and is configured to provide a first voltage;

the second power pin is physically deleted from being connected to said second power rail; and

the second power rail is coupled to a remaining cell of said plurality of cells and is configured to provide a second voltage.

2. The circuit of claim 1, wherein said second power rail is separated from said first power rail by an intervening dielectric.

3. The circuit of claim 1, wherein said first voltage and said second voltage have substantially a same value.

4. The circuit of claim 1, wherein said first and second power rails are adjacent or separated.

5. The circuit of claim 1, wherein said first and second power rails are in a same metal layer.

6. The circuit of claim 1, wherein said first and second power rails are in different metal layers.

7. The circuit of claim 1, wherein at least two of said plurality of cells that are coupled to said first power rail are adjacent to each other.

8. A method of distributing power to a plurality of cells in an integrated circuit layout, the method comprising:

routing, using processor circuitry, each of a plurality of power rails in said integrated circuit layout, said plurality of power rails comprising a first power rail configured to provide a first voltage and a second power rail configured to provide a second voltage;

placing said plurality of cells in said integrated circuit layout, wherein each of said plurality of cells is configured for connection to anyone of said first power rail and said second power rail, wherein a first subset of cells of the plurality of cells has first and second power pins, and wherein the first power pin is configured for connection to the first power rail and the second power pin is configured for connection to the second power rail;

coupling the first subset of cells to said first power rail through the first power pin; and

physically deleting the second power pin from being connected to said second power rail.

9. The method of claim 8 further comprising:

coupling a first independent voltage source to said first power rail; and

coupling a second independent voltage source to said second power rail, wherein the first and second power rails are each configured for connection to each of the plurality of cells.

10. The method of claim 8, wherein a distance between said first and second power rails is approximately 10-20 microns.

11. The method of claim 8, wherein:

each of the plurality of cells is associated with a first power pin configured for connection to the first power rail and a second power pin configured for connection to the second power rail; and

a second subset of cells of the plurality of cells is selectively coupled to the second power rail through the second power pin.

12. The method of claim 8, wherein:

at least one of the plurality of cells has;

reconfigurable power and/or ground pins;

or

multiple copies of power and/or ground pins at different locations in the cell; and

after the power rails are routed, all but one power pin and all but one ground pin is removed from the at least one of the plurality of cells.

13. The method of claim 8, wherein the plurality of cells are placed in voltage rows such that a majority of the voltage rows include only cells that are to be connected to a same power rail, further comprising grouping cells connected to the same power rail locally close to each other in the same or adjacent voltage rows.

14. The method of claim 8, wherein at least one of the plurality of cells is a dual-rail standard cell, further comprising routing a voltage column configured to provide one of the first and second voltages to at least the dual-rail standard cell.

15. The method of claim 8, wherein the circuitry is configured to connect said first power rail to said first subset of cells and to connect said second power rail to a second subset of cells.

16. The method of claim 8, wherein the circuitry is configured to place said first power rail adjacent to said second power rail.

17. A method of designing a power grid in an integrated circuit layout, the method comprising:

routing, using processor circuitry, a global power grid in said integrated circuit layout, said global power grid comprising a plurality of power straps in one or more first metallization layers, said plurality of power straps comprising a first power strap configured to provide a first voltage and a second power strap configured to provide a second voltage;

routing a virtual local power grid, said virtual local power grid comprising a plurality of power nets coupled to one of said first and second power straps;

placing a plurality of cells in said integrated circuit layout, wherein each of said plurality of cells is configured for connection to anyone of first and second power nets, wherein the first power net is coupled to the first power strap and the second power net is coupled to said second power strap, wherein a first subset of cells of the plurality of cells has first and second power pins, and wherein the first power pin is configured for connection to the first power net and the second power pin is configured for connection to the second power net;

coupling the first subset of cells to said first power net through the first power pin;

physically deleting the second power pin from being connected to said second power net; and

converting said virtual local power grid to an actual local power grid.

18. The method of claim 17, wherein routing the virtual local power grid further comprises routing a voltage column configured to provide one of the first and second voltages to at least a subset of said plurality of cells.

19. The method of claim 17, wherein each of said plurality of power nets comprises a metal line in one or more second metallization layers.

20. The method of claim 17, wherein each of said one or more first metallization layers is in a higher metallization level than each of said metal lines in said one or more second metallization layers.

21. The method of claim 17, further comprising estimating an impact of the actual local power grid from the virtual local power grid using a place and route tool, wherein the plurality of cells are placed in voltage rows such that the cells in a given voltage row are connected to one of a first power rail or a second power rail, and converting the virtual local power grid to the actual local power grid comprises generating the actual local power grid for each voltage row, based on a determination of whether the voltage row needs one power rail or more than one power rail.