Method of fabricating a semiconductor device having a defined minimum gate spacing between adjacent gate structures

• US 8,635,573 B2
• Filed: 08/01/2011
• Issued: 01/21/2014
• Est. Priority Date: 08/01/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chuang, Hak-Lay, Zhu, Ming, Chen, Po-Nien, Young, Bao-Ru
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US13/195,628
• Publication Number:
  US 20130032884A1
• Time in Patent Office: 904 Days
• Field of Search: 438587-588, 716110-111, 716118-119, 716/122
• US Class Current: 716/122
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 2223/58 Structural electrical arrangements for semiconductor devices not otherwise provided for
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0218 of field effect structures
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (√{square root over (W*W+L*L)})/10. The second gate structure is a next adjacent gate structure to the first gate structure. A method and apparatus for designing an integrated circuit including implementing a design rule defining the separation of gate structures is also described. In embodiments, the distance of separation is implemented for gate structures that are larger relative to other gate structures on the substrate (e.g., greater than 3 μm²).

Claims

1. A method of integrated circuit fabrication, comprising:

forming a first gate structure having a width (W) and a length (L), wherein W and L are provided in a unit of microns;

forming a second gate structure separated a distance from a first side of the first gate structure, wherein the distance of separation is greater than;

2. The method of claim 1, wherein the distance of separation is less than approximately 500 nm.

3. The method of claim 1, wherein the distance of separation is determined by a design rule associated with the IC fabrication.

4. The method of claim 1, wherein the first gate structure has an area of greater than approximately 3 μ

m².

5. The method of claim 1, further comprising:

forming a third gate structure, wherein the third gate structure has an area of less than approximately 3 μ

m², and wherein the first gate structure and the second gate structure have an area of greater than approximately 3 μ

m².

6. The method of claim 1, wherein the first gate structure and the second gate structure include polysilicon.

7. The method of claim 6, wherein the first gate structure and the second gate structure are sacrificial gate structures.

8. The method of claim 1, further comprising:

forming a dielectric layer between the first gate structure and the second gate structure;

removing the first gate structure and the second gate structure to form a first and second opening in the dielectric layer; and

forming a metal gate structure in each of the first and second openings.

9. The method of claim 8, wherein the forming the metal gate includes:

forming a layer of high-k dielectric in the first and second opening;

forming a layer of metal in the first and second opening; and

performing a chemical mechanical polishing (CMP) process of the layer of metal.

10. A method of integrated circuit fabrication, comprising:

receiving a pattern defining a first gate structure and a second gate structure wherein at least one of the first and second gate structures have a width (W) and a length (L), wherein W and L are provided in a unit of microns;

performing a design rule check on the pattern, wherein the design rule check requires a distance of separation between the first and second gate structures is greater than;

11. The method of claim 10, wherein the distance of separation is less than approximately 500 nm.

12. The method of claim 10, wherein the first gate structure is defined by L and W, and wherein the product of L and W is greater than approximately 3 μ

m².

13. The method of claim 10, wherein the modified pattern further defines a third gate structure spaced a distance from the second gate structure, wherein the third gate structure has an area of less than approximately 3 μ

m², and wherein the first gate structure and the second gate structure have an area of greater than approximately 3 μ

m².

14. The method of claim 10, wherein the fabricating the modified pattern includes forming the first gate structure and the second gate structure using polysilicon.

15. A method of integrated circuit fabrication, comprising:

forming a first gate structure having a width (W) and a length (L), wherein W * L is greater than approximately 3 microns;

forming a second gate structure separated a distance of separation from a closest side of the first gate structure, wherein the distance of separation is greater than;

16. The method of claim 15, further comprising:

forming a third gate structure spaced a second distance from the second gate structure, wherein the third gate structure has an area of less than approximately 3 μ

m^2.

17. The method of claim 16, wherein the second distance is less than the distance of separation.

18. The method of claim 16, wherein the second distance is between approximately 100 nanometers (nm) and approximately 200 nm.