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Memory-aware scheduling for NUMA architectures

  • US 8,635,626 B2
  • Filed: 12/29/2010
  • Issued: 01/21/2014
  • Est. Priority Date: 12/29/2010
  • Status: Active Grant
First Claim
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1. A system including instructions recorded on a non-transitory computer-readable medium, the system comprising:

  • a core list generator configured to generate, for each designated core of a Non-Uniform Memory Access (NUMA) architecture, and based on a topology of the NUMA architecture, a proximity list listing non-designated cores in an order corresponding to latencies for transferring state information stored in association with threads to the non-designated cores from the designated core, the core list generator being configured to generate the proximity list by taking into account a number of, and connections between, a plurality of sockets included in the NUMA architecture, each socket including one or more cores; and

    a core selector configured to determine, at a target core and during execution of a plurality of threads, that the target core is executing an insufficient number of the plurality of threads, and further configured to select a source core at the target core, according to the proximity list associated therewith, for subsequent transfer of a transferred thread and the transferred thread'"'"'s associated state information from the selected source core to the target core for execution thereon.

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