Method for manufacturing semiconductor device

• US 8,637,347 B2
• Filed: 07/01/2010
• Issued: 01/28/2014
• Est. Priority Date: 07/03/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Oikawa, Yoshiaki, Okazaki, Kenichi, Maruyama, Hotaka
• Primary Examiner(s): Tran, Thanh Y
• Application Number:
  US12/828,465
• Publication Number:
  US 20110003429A1
• Time in Patent Office: 1,307 Days
• Field of Search: 257/E29.121, 257/E29.094, 257/59, 257/72, 257/622, 257/411, 257/43, 257/78, 257/614, 257/40, 257/79, 257/80, 257/81, 257/83, 257/84, 257/99, 257/103, 257/257, 257/258, 257/290, 257/291, 257/390, 257/202, 438/719, 438/151, 438/723, 438/756, 438/689, 438/685, 438/683, 438/149, 438/158, 438/104, 438/761, 438/762, 438/22, 438/24, 438/34, 438/46, 438/48, 438/128, 438/130, 438/278, 438/275, 438/290, 438/85, 438/754, 438/161, 438/587
• US Class Current: 438/104
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Disclosed is a method to manufacture a thin film transistor having an oxide semiconductor as a channel formation region. The method includes; forming an oxide semiconductor layer over a gate insulating layer; forming a source and drain electrode layers over and in contact with the oxide semiconductor layer so that at least portion of the oxide semiconductor layer is exposed; and forming an oxide insulating film over and in contact with the oxide semiconductor layer. The exposed portion of the oxide semiconductor may be exposed to a gas containing oxygen in the presence of plasma before the formation of the oxide insulating film. The method allows oxygen to be diffused into the oxide semiconductor layer, which contributes to the excellent characteristics of the thin film transistor.

Claims

1. A method for manufacturing a semiconductor device, the method comprising the steps of:

forming a gate electrode layer over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming an oxide semiconductor layer over the gate insulating layer;

forming a metal film over and in contact with the oxide semiconductor layer;

etching the metal film to form an exposed region in the oxide semiconductor layer and to form a source electrode layer and a drain electrode layer over and in contact with the oxide semiconductor layer;

performing plasma treatment on the exposed region in the presence of a gas containing an oxygen element; and

forming an oxide insulating film over and in contact with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer,

wherein the etching is performed so that the exposed region of the oxide semiconductor layer has a smaller thickness than a region of the oxide semiconductor layer which is covered with the source electrode layer or the drain electrode layer.

2. The method according to claim 1,

wherein the oxide semiconductor layer comprises indium, zinc, oxygen, and a metal which is selected from Ga, Fe, Ni, Mn, and Co.

3. The method according to claim 1,

wherein the oxide semiconductor layer has a composition expressed by InMO₃(ZnO)_m,

wherein M is a metal selected from Ga, Fe, Ni, Mn, and Co, and

wherein m is larger than 0.

4. The method according to claim 1, wherein the gas is selected from an oxygen gas, a nitrogen oxide gas, and a nitrogen dioxide gas.

5. The method according to claim 1, further comprising a heat treatment step,

wherein the heat treatment step is performed from the plasma treatment until the formation of the oxide insulating film.

6. The method according to claim 1,

wherein the oxide insulating film comprises silicon.

7. The method according to claim 1,

wherein a side surface of the exposed region and at least one of side surfaces of the source electrode layer and the drain electrode layer are coplanar.

8. The method according to claim 1,

wherein the etching is performed so that the whole of the oxide semiconductor layer covers part of the gate electrode layer.

9. A method for manufacturing a semiconductor device, the method comprising the steps of:

forming a gate electrode layer over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming an oxide semiconductor layer over the gate insulating layer;

forming a metal film over and in contact with the oxide semiconductor layer;

etching the metal film to form an exposed region in the oxide semiconductor layer and to form a source electrode layer and a drain electrode layer over and in contact with the oxide semiconductor layer;

introducing the substrate into a chamber;

introducing a gas containing an oxygen element into the chamber with the substrate left in the chamber;

generating plasma in the presence of the gas in the chamber with the substrate left in the chamber; and

forming an oxide insulating film over and in contact with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer in the chamber,

wherein the etching is performed so that the exposed region of the oxide semiconductor layer has a smaller thickness than a region of the oxide semiconductor layer which is covered with the source electrode layer or the drain electrode layer.

10. The method according to claim 9,

wherein the oxide semiconductor layer comprises indium, zinc, oxygen, and a metal which is selected from Ga, Fe, Ni, Mn, and Co.

11. The method according to claim 9,

wherein the oxide semiconductor layer has a composition expressed by InMO₃(ZnO)_m,

wherein M is a metal selected from Ga, Fe, Ni, Mn, and Co, and

wherein m is larger than 0.

12. The method according to claim 9, wherein the gas is selected from an oxygen gas, a nitrogen oxide gas, and a nitrogen dioxide gas.

13. The method according to claim 9, further comprising a heat treatment step,

wherein the heat treatment step is performed after the substrate is introduced to the chamber and until the formation of the oxide insulating film is completed.

14. The method according to claim 9,

wherein the oxide insulating film comprises silicon.

15. The method according to claim 9,

wherein a side surface of the exposed region and at least one of side surfaces of the source electrode layer and the drain electrode layer are coplanar.

16. The method according to claim 9,

wherein the etching is performed so that the whole of the oxide semiconductor layer covers part of the gate electrode layer.

17. A method for manufacturing a semiconductor device, the method comprising the steps of:

forming a gate electrode layer over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming an oxide semiconductor layer over the gate insulating layer;

forming a metal film over and in contact with the oxide semiconductor layer;

etching the metal film to form an exposed region in the oxide semiconductor layer and to form a source electrode layer and a drain electrode layer over and in contact with the oxide semiconductor layer;

introducing the substrate into a chamber;

evacuating the chamber with the substrate left in the chamber;

introducing a nitrogen gas to the chamber with the substrate left in the chamber;

heating the substrate in the chamber with the substrate left in the chamber;

introducing a gas containing an oxygen element into the chamber with the substrate left in the chamber;

introducing plasma into the chamber in the presence of the gas with the substrate left in the chamber; and

forming an oxide insulating film over and in contact with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer in the chamber,

wherein the etching is performed so that the exposed region of the oxide semiconductor layer has a smaller thickness than a region of the oxide semiconductor layer which is covered with the source electrode layer or the drain electrode layer.

18. The method according to claim 17,

wherein the oxide semiconductor layer comprises indium, zinc, oxygen, and a metal which is selected from Ga, Fe, Ni, Mn, and Co.

19. The method according to claim 17,

wherein the oxide semiconductor layer has a composition expressed by InMO₃(ZnO)_m,

wherein M is a metal selected from Ga, Fe, Ni, Mn, and Co, and

wherein m is larger than 0.

20. The method according to claim 17,

wherein the gas is selected from an oxygen gas, a nitrogen oxide gas, and a nitrogen dioxide gas.

21. The method according to claim 17,

wherein the heating step of the substrate is continued until the formation of the oxide insulating film is completed.

22. The method according to claim 17,

wherein the oxide insulating film comprises silicon.

23. The method according to claim 17,

wherein the introduction of plasma is performed using a remote plasma apparatus.

24. The method according to claim 17,

wherein a side surface of the exposed region and at least one of side surfaces of the source electrode layer and the drain electrode layer are coplanar.

25. The method according to claim 17,

wherein the etching is performed so that the whole of the oxide semiconductor layer covers part of the gate electrode layer.

26. A method for manufacturing a semiconductor device, the method comprising the steps of:

forming a gate electrode layer over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming an oxide semiconductor layer over the gate insulating layer;

forming a source electrode layer and a drain electrode layer over the oxide semiconductor layer; and

performing plasma treatment on the oxide semiconductor layer in the presence of a gas containing an oxygen element,

wherein a thickness of the oxide semiconductor layer in a region between the source electrode layer and the drain electrode layer is smaller than a thickness of the oxide semiconductor layer in a region covered with the source electrode layer or the drain electrode layer.

27. The method according to claim 26,

wherein the source electrode layer and the drain electrode layer are formed so as to be in contact with the oxide semiconductor layer.

28. The method according to claim 26, further comprising a step of forming an oxide insulating film over and in contact with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer.

29. The method according to claim 28, further comprising a heat treatment step,

wherein the heat treatment step is performed from the plasma treatment until the formation of the oxide insulating film.

30. The method according to claim 28,

wherein the oxide insulating film comprises silicon.

31. The method according to claim 26,

wherein the oxide semiconductor layer comprises indium, zinc, oxygen, and a metal which is selected from Ga, Fe, Ni, Mn, and Co.

32. The method according to claim 26, wherein the oxide semiconductor layer has a composition expressed by InMO₃(ZnO)_m,

wherein M is a metal selected from Ga, Fe, Ni, Mn, and Co, and

wherein m is larger than 0.

33. The method according to claim 26,

wherein the gas is selected from an oxygen gas, a nitrogen oxide gas, and a nitrogen dioxide gas.

34. The method according to claim 26,

wherein a side surface of the region between the source electrode layer and the drain electrode layer and at least one of side surfaces of the source electrode layer and the drain electrode layer are coplanar.

35. The method according to claim 26,

wherein the oxide semiconductor layer is formed so that the whole of the oxide semiconductor layer covers part of the gate electrode layer.