Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states

• US 8,637,366 B2
• Filed: 09/29/2004
• Issued: 01/28/2014
• Est. Priority Date: 12/19/2002
• Status: Active Grant

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Herner, S. Brad, Walker, Andrew J.
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): GOODWIN, DAVID J
• Application Number:
  US10/955,549
• Publication Number:
  US 20050052915A1
• Time in Patent Office: 3,408 Days
• Field of Search: 438/258, 438/257, 438/593
• US Class Current: 438/257
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Abstract

A memory cell according to the present invention comprises a bottom conductor, a doped semiconductor pillar, and a top conductor. The memory cell does not include a dielectric rupture antifuse separating the doped semiconductor pillar from either conductor, or within the semiconductor pillar. The memory cell is formed in a high-impedance state, in which little or no current flows between the conductors on application of a read voltage. Application of a programming voltage programs the cell, converting the memory cell from its initial high-impedance state to a low-impedance state. A monolithic three dimensional memory array of such cells can be formed, comprising multiple memory levels, the levels monolithically formed above one another.

Claims

1. A method for forming a memory cell, the method comprising:

forming a first elongate conductor having a top layer;

forming a vertical polycrystalline or amorphous pillar, the pillar consisting essentially of semiconductor material and comprising a bottom heavily doped region of a first conductivity type, a center lightly doped or intrinsic region disposed on the bottom heavily doped region, and a top heavily doped region of a second conductivity type disposed on the center lightly doped or intrinsic region, the pillar formed over and in electrical contact with the first conductor; and

forming a second conductor over the pillar, the second conductor having a bottom layer, wherein the pillar is in electrical contact with the second conductor,

wherein;

the top layer of the first elongate conductor does not comprise semiconductor material,

the bottom layer of the second conductor does not comprise semiconductor material,

the memory cell does not include a dielectric rupture antifuse,

the pillar comprises a silicon-germanium alloy, and

the bottom heavily doped region and the top heavily doped region have a higher ratio of silicon to germanium than does the center lightly doped or intrinsic region.

2. The method of claim 1 wherein the top layer of the first conductor comprises a metal.

3. The method of claim 1 wherein the top layer of the first conductor comprises a silicide.

4. The method of claim 1 wherein the top layer of the first conductor comprises titanium nitride, tantalum nitride, or tungsten nitride.

5. The method of claim 1 wherein the pillar comprises silicon.

6. The method of claim 1 wherein the pillar comprises germanium.

7. The method of claim 1 wherein the step of forming the pillar comprises:

depositing a layer stack of semiconductor material; and

etching and patterning the layer stack to form the pillar.

8. A method for forming a memory cell, the method comprising:

forming a first conductor having a top layer;

forming a layer stack consisting essentially of doped polycrystalline semiconductor material comprising a bottom heavily doped region of a first conductivity type, a center lightly doped or intrinsic region disposed on the bottom heavily doped region, and a top heavily doped region of a second conductivity type disposed on the center lightly doped or intrinsic region;

patterning and etching the layer stack to form a semiconductor pillar in electrical contact with the top layer of the first conductor;

forming a second conductor over the pillar, the second conductor having a bottom layer, wherein the pillar is in electrical contact with the second conductor,

wherein;

the top layer of the first conductor does not comprise semiconductor material,

the bottom layer of the second conductor does not comprise semiconductor material,

the memory cell does not include a dielectric rupture antifuse,

the pillar comprises a silicon-germanium alloy, and

the bottom heavily doped region and the top heavily doped region have a higher ratio of silicon to germanium than does the center lightly doped or intrinsic region.

9. The method of claim 8 wherein the pillar comprises silicon.

10. The method of claim 8 wherein the pillar comprises germanium.

11. The method of claim 8 wherein the pillar comprises conductivity-enhancing dopants.

12. The method of claim 11 wherein the pillar comprises both a p-type region and an n-type region.

13. The method of claim 8 wherein the top layer of the bottom conductor comprises a metal.

14. The method of claim 8 wherein the top layer of the bottom conductor comprises a silicide.