Fabrication of MOS device with varying trench depth

• US 8,637,368 B2
• Filed: 07/27/2012
• Issued: 01/28/2014
• Est. Priority Date: 02/11/2005
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Wang, Xiaobin
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US13/559,975
• Publication Number:
  US 20120302021A1
• Time in Patent Office: 550 Days
• Field of Search: 438/259, 438/589
• US Class Current: 438/259
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; disposing gate material in the gate trench; forming a body in the epitaxial layer; forming a source in the body; forming an active region contact trench that has a varying trench depth; and disposing a contact electrode within the active region contact trench. Forming the active region contact trench includes performing a first etch to form a first contact trench depth associated with a first region, and performing a second etch to form a second contact trench depth associated with a second region. The first contact trench depth is substantially different from the second contact trench depth.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a gate trench in an epitaxial layer overlaying a semiconductor substrate;

disposing gate material in the gate trench;

forming a body in the epitaxial layer;

forming a source in the body;

forming an active region contact trench that has a varying trench depth, including;

performing a first etch to form a first contact trench depth associated with a first region; and

performing a second etch to form a second contact trench depth associated with a second region;

wherein

the first contact trench depth is substantially different from the second contact trench depth; and

disposing a contact electrode within the active region contact trench.

2. The method of claim 1, wherein:

performing the first etch includes;

applying a first mask; and

etching to achieve the first contact trench depth; and

performing the second etch includes;

applying a second mask; and

etching to achieve the second contact trench depth.

3. The method of claim 1, wherein a Schottky contact is formed in the first region.

4. The method of claim 1, further comprising forming a drain on the back of the semiconductor substrate;

wherein a Schottky contact is formed in the first region by the contact electrode and a drain region.

5. The method of claim 1, further comprising forming a drain on the back of the semiconductor substrate;

wherein a Schottky contact is formed in the first region by the contact electrode and a drain region, and the method further comprises forming a Schottky barrier controlling layer in the epitaxial layer below the Schottky contact.

6. The method of claim 1, wherein a Schottky contact is formed in the first region, and the method further comprises forming an anti-punch through implant on a side wall of the first region of the active region contact trench.

7. The method of claim 6, wherein forming the anti-punch through implant includes forming a heavily doped region.

8. The method of claim 7, wherein a body contact is formed in the second region by the contact electrode and the heavily doped region.

9. The method of claim 1, wherein the gate trench is formed in a striped pattern.

10. The method of claim 1, wherein the gate trench is formed in a grid pattern.

11. The method of claim 1, wherein:

the gate trench is formed in a grid pattern such that the semiconductor device is a closed cell device having a width and a length; and

forming the active region contact trench includes forming the first contact trench depth and the second contact trench depth along a length-wise cross section.

12. The method of claim 1, wherein an area ratio of the first region and the second region is controlled to meet both an unclamped inductive switching (UIS) recovery requirement and a diode recovery requirement.