Semiconductor device and method of manufacturing the same

• US 8,637,864 B2
• Filed: 10/01/2012
• Issued: 01/28/2014
• Est. Priority Date: 10/13/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Saito, Toshihiko, Isobe, Atsuo, Hanaoka, Kazuya, Koezuka, Junichi, Sasagawa, Shinya, Kurata, Motomu, Ishizuka, Akihiro
• Primary Examiner(s): Lee, Calvin
• Assistant Examiner(s): STOWE, SCOTT C
• Application Number:
  US13/632,635
• Publication Number:
  US 20130092925A1
• Time in Patent Office: 484 Days
• Field of Search: 257/43, 257/57, 257/E29.296, 438/104, 438/151
• US Class Current: 257/43
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

A miniaturized transistor is provided with high yield. Further, a semiconductor device which has high on-state characteristics and which is capable of high-speed response and high-speed operation is provided. In the semiconductor device, an oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an insulating layer, a conductive film, and an interlayer insulating layer are stacked in this order. A source electrode layer and a drain electrode layer are formed in a self-aligned manner by cutting the conductive film so that the conductive film over the gate electrode layer and the conductive layer is removed and the conductive film is divided. An electrode layer which is in contact with the oxide semiconductor layer and overlaps with a region in contact with the source electrode layer and the drain electrode layer is provided.

Claims

1. A semiconductor device comprising:

a first electrode layer and a second electrode layer;

an oxide semiconductor layer over the first electrode layer and the second electrode layer, wherein the oxide semiconductor layer includes a first region electrically connected to the first electrode layer, a second region electrically connected to the second electrode layer, and a channel formation region between the first region and the second region;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode layer over the gate insulating layer, wherein the gate electrode layer overlaps with the channel formation region;

a first insulating layer over the gate electrode layer;

sidewall insulating layers covering side surfaces of the gate electrode layer and side surfaces of the first insulating layer;

a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor layer, side surfaces of the gate insulating layer, and side surfaces of the sidewall insulating layer;

a second insulating layer over the source electrode layer and the drain electrode layer;

a third insulating layer over the first insulating layer, the sidewall insulating layers, the source electrode layer, the drain electrode layer, and the second insulating layer; and

a first wiring layer electrically connected to the first region through a first opening and a second wiring layer electrically connected to the second region through a second opening, wherein the first opening and the second opening are formed in the second insulating layer and the third insulating layer, and

wherein heights of top surfaces of the source electrode layer and the drain electrode layer are lower than heights of top surfaces of the first insulating layer, the sidewall insulating layer, and the second insulating layer, and are higher than a height of a top surface of the gate electrode layer.

2. The semiconductor device according to claim 1, wherein the first electrode layer and the second electrode layer are provided in a base insulating layer, and top surfaces of the first electrode layer and the second electrode layer are exposed from the base insulating layer.

3. The semiconductor device according to claim 1, wherein a thickness of the first electrode layer and the second electrode layer is greater than a thickness of the oxide semiconductor layer.

4. The semiconductor device according to claim 1, wherein the first electrode layer and the second electrode layer are formed in contact with a top surface of a base insulating layer.

5. The semiconductor device according to claim 1, wherein the second insulating layer comprises an aluminum oxide layer in contact with the source electrode layer and the drain electrode layer.

6. The semiconductor device according to claim 1, wherein a surface on which the channel formation region is to be formed has planarity.

7. The semiconductor device according to claim 1,

wherein the first wiring layer overlaps with the first electrode layer, and

wherein the second wiring layer overlaps with the second electrode layer.

8. The semiconductor device according to claim 1,

wherein the first wiring layer is electrically connected to the first region through the source electrode layer, and

wherein the second wiring layer is electrically connected to the second region through the drain electrode layer.

9. The semiconductor device according to claim 1, wherein a resistance of the first region and a resistance of the second region are lower than a resistance of the channel formation region.

10. A semiconductor device comprising:

a first electrode layer and a second electrode layer;

an oxide semiconductor layer over the first electrode layer and the second electrode layer, wherein the oxide semiconductor layer includes a first region electrically connected to the first electrode layer, a second region electrically connected to the second electrode layer, and a channel formation region between the first region and the second region;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode layer over the gate insulating layer, wherein the gate electrode layer overlaps with the channel formation region;

sidewall insulating layers covering side surfaces of the gate electrode layer;

a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor layer, side surfaces of the gate insulating layer, and side surfaces of the sidewall insulating layer;

a first insulating layer over the source electrode layer and the drain electrode layer;

a second insulating layer over and in contact with the gate electrode layer, the sidewall insulating layers, the source electrode layer, the drain electrode layer, and the first insulating layer; and

a first wiring layer electrically connected to the first region through a first opening and a second wiring layer electrically connected to the second region through a second opening, wherein the first opening and the second opening are formed in the first insulating layer and the second insulating layer.

11. The semiconductor device according to claim 10, wherein the first electrode layer and the second electrode layer are provided in a base insulating layer, and top surfaces of the first electrode layer and the second electrode layer are exposed from the base insulating layer.

12. The semiconductor device according to claim 10, wherein a thickness of the first electrode layer and the second electrode layer is greater than a thickness of the oxide semiconductor layer.

13. The semiconductor device according to claim 10, wherein the first electrode layer and the second electrode layer are formed in contact with a top surface of a base insulating layer.

14. The semiconductor device according to claim 10, wherein the second insulating layer comprises an aluminum oxide layer in contact with the source electrode layer and the drain electrode layer.

15. The semiconductor device according to claim 10, wherein a surface on which the channel formation region is to be formed has planarity.

16. The semiconductor device according to claim 10,

wherein the first wiring layer overlaps with the first electrode layer, and

wherein the second wiring layer overlaps with the second electrode layer.

17. The semiconductor device according to claim 10,

wherein the first wiring layer is electrically connected to the first region through the source electrode layer, and

wherein the second wiring layer is electrically connected to the second region through the drain electrode layer.

18. The semiconductor device according to claim 10, wherein a resistance of the first region and a resistance of the second region are lower than a resistance of the channel formation region.