Semiconductor device

• US 8,637,865 B2
• Filed: 02/15/2013
• Issued: 01/28/2014
• Est. Priority Date: 07/02/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi
• Primary Examiner(s): Quach, Tuan N.
• Application Number:
  US13/767,904
• Publication Number:
  US 20130153894A1
• Time in Patent Office: 347 Days
• Field of Search: 257/67, 257/68, 257/71, 257/74, 257/296, 257/369, 257/E27.034, 257/E29.1, 257/E29.296, 257/E25.013, 257/43
• US Class Current: 257/43
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: H10B 99/22 including field-effect components

Abstract

An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

Claims

1. A semiconductor device comprising:

a first transistor comprising a first channel formation region comprising a single crystal silicon;

a second transistor comprising a second channel formation region comprising an oxide semiconductor material, over the first transistor;

a capacitor over the first transistor; and

a third transistor comprising a third channel formation region comprising the oxide semiconductor material, over the second transistor,

wherein the third transistor overlaps with at least one of the first transistor and the second transistor,

wherein a gate of the first transistor is electrically connected to one of a source or a drain of the second transistor and the capacitor, and

wherein the oxide semiconductor material comprises indium.

2. The semiconductor device according to claim 1, wherein one of a source or a drain of the first transistor is electrically connected to the other one of the source or the drain of the second transistor.

3. The semiconductor device according to claim 1, wherein the gate of the first transistor is in contact with the one of the source or the drain of the second transistor.

4. The semiconductor device according to claim 1, wherein the third transistor overlaps with the first transistor and the capacitor.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor material further comprises gallium and zinc.

6. The semiconductor device according to claim 1, wherein off-state current of the second transistor is lower than or equal to 1×

10<sup>−

19</sup> A at 25°

C.

7. A semiconductor device comprising:

a first transistor comprising a first channel formation region comprising a single crystal silicon;

a second transistor over the first transistor, the second transistor comprising;

an oxide semiconductor layer comprising a second channel formation region, the second channel formation region comprising an oxide semiconductor material;

a source and a drain over the oxide semiconductor layer;

a gate insulating layer over the source and the drain; and

a gate over the gate insulating layer, the gate overlapping with the source and the drain,

a capacitor over the first transistor; and

a third transistor comprising a third channel formation region comprising the oxide semiconductor material, over the second transistor,

wherein the third transistor overlaps with at least one of the first transistor and the second transistor,

wherein a gate of the first transistor is electrically connected to one of the source or the drain of the second transistor and the capacitor, and

wherein the oxide semiconductor material comprises indium.

8. The semiconductor device according to claim 7, wherein one of a source or a drain of the first transistor is electrically connected to the other one of the source or the drain of the second transistor.

9. The semiconductor device according to claim 7, wherein the gate of the first transistor is in contact with the one of the source or the drain of the second transistor.

10. The semiconductor device according to claim 7, wherein the third transistor overlaps with the first transistor and the capacitor.

11. The semiconductor device according to claim 7, wherein the oxide semiconductor material further comprises gallium and zinc.

12. The semiconductor device according to claim 7, wherein off-state current of the second transistor is lower than or equal to 1×

10<sup>−

19</sup> A at 25°

C.

13. A semiconductor device comprising:

a first transistor comprising a first channel formation region comprising a single crystal silicon;

a second transistor comprising a second channel formation region comprising an oxide semiconductor material, over the first transistor;

a first capacitor over the first transistor;

a third transistor comprising a third channel formation region comprising the oxide semiconductor material, over the second transistor;

a fourth transistor comprising a fourth channel formation region comprising the oxide semiconductor material, over the third transistor; and

a second capacitor over the third transistor,

wherein the third transistor overlaps with at least one of the first transistor and the second transistor,

wherein a gate of the first transistor is electrically connected to one of a source or a drain of the second transistor and the first capacitor, and

wherein the oxide semiconductor material comprises indium.

14. The semiconductor device according to claim 13, wherein one of a source or a drain of the first transistor is electrically connected to the other one of the source or the drain of the second transistor.

15. The semiconductor device according to claim 13, wherein the gate of the first transistor is in contact with the one of the source or the drain of the second transistor.

16. The semiconductor device according to claim 13, wherein the third transistor overlaps with the first transistor and the first capacitor.

17. The semiconductor device according to claim 13, wherein the fourth transistor overlaps with the third transistor.

18. The semiconductor device according to claim 13, wherein a gate of the third transistor is electrically connected to one of a source or a drain of the fourth transistor and the second capacitor.

19. The semiconductor device according to claim 13, wherein the oxide semiconductor material further comprises gallium and zinc.

20. The semiconductor device according to claim 13, wherein off-state current of the second transistor is lower than or equal to 1×

10<sup>−

19</sup> A at 25°

C.

21. A semiconductor device comprising:

a first transistor comprising a first channel formation region comprising a single crystal silicon;

an insulating layer over the first transistor;

a second transistor comprising a second channel formation region comprising an oxide semiconductor material, over the insulating layer;

a capacitor over the insulating layer; and

a third transistor comprising a third channel formation region comprising the oxide semiconductor material, over the insulating layer,

wherein the second transistor overlaps with at least one of the first transistor and the third transistor,

wherein a gate of the second transistor is electrically connected to one of a source or a drain of the third transistor and the capacitor, and

wherein the oxide semiconductor material comprises indium.

22. The semiconductor device according to claim 21, wherein the third transistor is formed over the second transistor.

23. The semiconductor device according to claim 21, wherein one of a source or a drain of the second transistor is electrically connected to the other one of the source or the drain of the third transistor.

24. The semiconductor device according to claim 21, wherein the gate of the second transistor is in contact with the one of the source or the drain of the third transistor.

25. The semiconductor device according to claim 21, wherein the second transistor overlaps with the first transistor.

26. The semiconductor device according to claim 21, wherein the third transistor overlaps with the second transistor.

27. The semiconductor device according to claim 21, wherein the oxide semiconductor material further comprises gallium and zinc.

28. The semiconductor device according to claim 21,

wherein off-state current of the second transistor is lower than or equal to 1×

10<sup>−

19</sup> A at 25°

C., and

wherein off-state current of the third transistor is lower than or equal to 1×

10<sup>−

19</sup> A at 25°

C.