Transistor having recess channel and fabricating method thereof

• US 8,637,923 B2
• Filed: 06/24/2010
• Issued: 01/28/2014
• Est. Priority Date: 12/26/2006
• Status: Active Grant

• Current Assignee: SK Keyfoundry Incorporated (SK Hynix Inc.)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Cho, Cheol-Ho
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): Han, Jonathan
• Application Number:
  US12/822,936
• Publication Number:
  US 20100258865A1
• Time in Patent Office: 1,314 Days
• Field of Search: 257328-333, 257/339, 257/476, 257/565, 438268-274, 438/424
• US Class Current: 257/330
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A transistor includes a substrate including a trench, an insulation layer filled in a portion of the trench, the insulation layer having a greater thickness over an edge portion of a bottom surface of the trench than over a middle portion of the bottom surface of the trench, a gate insulation layer formed over inner sidewalls of the trench, the gate insulation layer having a thickness smaller than the insulation layer, and a gate electrode filled in the trench.

Claims

1. A transistor, comprising:

a substrate including a trench;

an insulation layer filled in a portion of the trench, wherein a top surface of the insulation layer comprises a ‘

V’

shape and a bottom surface comprising a rounded shape;

a gate insulation layer formed over inner sidewalls of the trench, the gate insulation layer having a width that is less than thicknesses of the insulation layer, the insulation layer being disposed below the gate insulation layer; and

a gate electrode filled in the trench.

2. The transistor of claim 1, wherein the insulation layer comprises an oxide-based material.

3. The transistor of claim 1, wherein the thicknesses of the insulation layer range from approximately 2,000 Å

to approximately 3,000 Å

.

4. The transistor of claim 1, wherein the substrate comprises:

a silicon substrate; and

an epitaxial layer formed over the silicon substrate.

5. The transistor of claim 4, wherein the trench is formed in the epitaxial layer.

6. The transistor of claim 1, wherein the trench has a depth ranging from approximately 1.2 μ

m to approximately 2.0 μ

m and a width ranging from approximately 0.38 μ

m to approximately 0.47 μ

m.

13. The transistor of claim 1, wherein a surface of the insulation layer is tapered from an edge portion of the surface of the insulation layer to a middle portion of the surface of the insulation layer.

14. The transistor of claim 13, wherein:

the tapered surface of the insulation layer is substantially linear from the edge portion of the tapered surface of the insulation layer to the middle portion of the tapered surface of the insulation layer; and

a bottom portion of the gate insulation layer is tapered to correspond to the edge portion of the tapered surface of the insulation layer.

18. The transistor of claim 1, wherein the insulation layer is disposed completely below the gate insulation layer.

7. A transistor, comprising:

a substrate including a trench;

an insulation layer filled in a portion of the trench, wherein a top surface of the insulation layer comprises a ‘

V’

shape and a bottom surface comprising a rounded shape;

a gate insulation layer formed over inner sidewalls of the trench, the gate insulation layer having a width that is less than thicknesses of the insulation layer, the insulation layer being disposed below the gate insulation layer; and

a gate electrode filled in the trench.

8. The transistor of claim 7, wherein the insulation layer comprises an oxide-based material.

9. The transistor of claim 7, wherein the thicknesses of the insulation layer range from approximately 2,000 Å

to approximately 3,000 Å

.

10. The transistor of claim 7, wherein the substrate comprises:

a silicon substrate; and

an epitaxial layer formed over the silicon substrate.

11. The transistor of claim 10, wherein the trench is formed in the epitaxial layer.

12. The transistor of claim 7, wherein the trench has a depth ranging from approximately 1.2 μ

m to approximately 2.0 μ

m and a width ranging from approximately 0.38 μ

m to approximately 0.47 μ

m.

19. The transistor of claim 7, wherein the insulation layer is disposed completely below the gate insulation layer.

15. A transistor, comprising:

a substrate comprising a trench;

an insulation layer in a portion of the trench, wherein a top surface of the insulation layer comprises a ‘

V’

shape and a bottom surface comprising a rounded shape;

a gate insulation layer formed over inner sidewalls of the trench and comprising a width that is less than thicknesses of the insulation layer, wherein the insulation layer is under the gate insulation layer; and

a gate electrode in the trench.

16. The transistor of claim 15, wherein the insulation layer comprises a thickness at a middle portion of the trench that is greater than a width of the insulation layer from an outer edge portion of the gate electrode to a surface of the trench that is nearest the outer edge portion of the gate electrode.

17. The transistor of claim 15, wherein the gate insulation layer comprises a width that is less than thicknesses of the insulation layer.

20. The transistor of claim 15, wherein the insulation layer is disposed completely below the gate insulation layer.