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Semiconductor structure with reduced junction leakage and method of fabrication thereof

  • US 8,637,955 B1
  • Filed: 08/31/2012
  • Issued: 01/28/2014
  • Est. Priority Date: 08/31/2012
  • Status: Active Grant
First Claim
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1. A method for forming a semiconductor structure, comprising:

  • providing a substrate;

    forming a first masking layer for a first device area of the substrate;

    epitaxially growing a first layer for a first field effect transistor, the first layer having a defined dopant concentration and grown to a preselected thickness;

    epitaxially growing a second layer for the first field effect transistor on the first layer, the second layer having a preselected dopant concentration and grown to a preselected thickness;

    removing the first masking layer for the first device area of the substrate;

    forming a second masking layer for a second device area of the substrate;

    epitaxially growing a first layer for a second field effect transistor, said first layer for the second field effect transistor having a defined dopant concentration and grown to a preselected thickness;

    epitaxially growing a second layer for the second field effect transistor on the first layer for the second field effect transistor, the second layer for the second field effect transistor having a preselected dopant concentration and a preselected thickness;

    removing the second masking layer for the second device area of the substrate;

    wherein at least some of the epitaxially grown layers form facets at edges of the first and second masking layers, the facets being eliminated by forming an isolation region in an area of the facets, the isolation region isolating the first field effect transistor from the second field effect transistor.

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