Semiconductor structure with reduced junction leakage and method of fabrication thereof

• US 8,637,955 B1
• Filed: 08/31/2012
• Issued: 01/28/2014
• Est. Priority Date: 08/31/2012
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: SuVolta, Inc.
• Inventors: Bakhishev, Teymur, Ranade, Pushkar, Hoffmann, Thomas, Shifren, Lucian, Scudder, Lance, Wang, Lingquan, Zhao, Dalong, Pradhan, Sameer
• Primary Examiner(s): Dickey, Thomas L
• Assistant Examiner(s): Schoenholtz, Joseph
• Application Number:
  US13/600,647
• Time in Patent Office: 515 Days
• Field of Search: None
• US Class Current: 257/506
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion, implantation.

Claims

1. A method for forming a semiconductor structure, comprising:

providing a substrate;

forming a first masking layer for a first device area of the substrate;

epitaxially growing a first layer for a first field effect transistor, the first layer having a defined dopant concentration and grown to a preselected thickness;

epitaxially growing a second layer for the first field effect transistor on the first layer, the second layer having a preselected dopant concentration and grown to a preselected thickness;

removing the first masking layer for the first device area of the substrate;

forming a second masking layer for a second device area of the substrate;

epitaxially growing a first layer for a second field effect transistor, said first layer for the second field effect transistor having a defined dopant concentration and grown to a preselected thickness;

epitaxially growing a second layer for the second field effect transistor on the first layer for the second field effect transistor, the second layer for the second field effect transistor having a preselected dopant concentration and a preselected thickness;

removing the second masking layer for the second device area of the substrate;

wherein at least some of the epitaxially grown layers form facets at edges of the first and second masking layers, the facets being eliminated by forming an isolation region in an area of the facets, the isolation region isolating the first field effect transistor from the second field effect transistor.

2. The method of claim 1, wherein said step of forming the first layer for the first field effect transistor includes forming said first layer according to a preselected dopant concentration by introducing dopant species into the epitaxial process.

3. The method of claim 1, wherein said step of forming the second layer for the first field effect transistor includes forming a substantially undoped channel layer.

4. The method of claim 2, wherein said step of forming the second layer for the second field effect transistor includes forming said second layer according to a preselected dopant concentration by introducing dopant species into the epitaxial process.

5. The method of claim 4, wherein said step of forming the second layer for the second field effect transistor includes forming a substantially undoped channel layer.

6. The method of claim 1, further comprising:

turning on a dopant source during epitaxial growth of the first layer for at least one of the first and second field effect transistors;

turning off a dopant source during epitaxial growth of the second layer for the at least one of the first and second field effect transistors.

7. The method of claim 6, wherein epitaxial growth is continuously performed for the first layer and the second layer for the at least one of the first and second field effect transistors.

8. The method of claim 6, wherein the thickness of the first layer and the second layer for the at least one of the first and second field effect transistors is determined by when the dopant source is turned off.

9. The method of claim 8, wherein the thickness for the second layer of the first field effect transistor is different than the thickness for the second layer of the second field effect transistor.

10. The method of claim 1, further comprising:

forming a threshold voltage control layer between the first layer and the second layer by epitaxial growth for at least one of the first and second field effect transistors, the threshold voltage control layer having a dopant concentration less than the first layer and greater than the second layer dopant concentration.

11. The method of claim 10, further comprising:

using a first doping condition during epitaxial growth of the first layer for the at least one of the first and second field effect transistors;

using a second doping condition during epitaxial growth of the threshold voltage control layer for the at least one of the first and second field effect transistors.

12. The method of claim 10, wherein epitaxial growth is continuously performed for the first layer, the threshold voltage control layer, and the second layer for the at least one of the first and second field effect transistors.

13. The method of claim 1, further comprising:

forming a threshold voltage control layer for the at least one of the first and second field effect transistors, the threshold voltage control layer having a dopant concentration that is less than the dopant concentration of the first layer for the at least one of the first and second field effect transistors, the threshold voltage control layer being formed by ion implantation.

14. A semiconductor structure, comprising:

a substrate;

a first field effect transistor formed on the substrate, the first field effect transistor comprising;

a first screen layer epitaxially grown on the substrate, the first screen layer having a first dopant and a first dopant concentration;

a first channel layer epitaxially grown on the first screen layer, the first channel layer being undoped;

a second field effect transistor, the second field effect transistor comprising;

a second screen layer epitaxial grown on the substrate, the second screen layer having a second dopant and a second dopant concentration;

a second channel layer epitaxially grown on the second screen layer, the second channel layer being undoped; and

an isolation region separating the first field effect transistor from the second field effect transistor, the isolation region being formed after the formation of the first and second screen layers and first and second channel layers for the first and second filed field effect transistors;

wherein a thickness of the first channel layer for the first field effect transistor is different than a thickness of the second channel layer for the second field effect transistor.

15. The semiconductor structure of claim 14, further comprising:

a threshold voltage control layer in the first field effect transistors, the threshold voltage control layer of the first field effect transistor being epitaxially grown on the first screen layer of the first field effect transistor, the threshold voltage control layer of the first field effect transistor having a dopant concentration less than the first screen layer first dopant concentration and greater than the first channel layer dopant concentration.

16. The semiconductor structure of claim 15, wherein the threshold voltage control layer is formed by ion implantation.

17. The semiconductor structure of claim 14, wherein the first channel layer and the first screen layer of the first field effect transistor are formed from a continuous epitaxial growth.

18. The semiconductor structure of claim 14, wherein the first screen layer or the second screen layer has a lower junction leakage due to epitaxial growth than a comparable ion implanted screen layer.

19. The semiconductor structure of claim 14, wherein a combined thickness for the first channel layer and the first screen layer of the first field effect transistor is a same thickness as a combined thickness for the second channel layer and the second screen layer of the second field effect transistor.

20. A semiconductor structure, comprising:

a substrate;

a first field effect transistor formed on the substrate, the first field effect transistor comprising;

a first screen layer epitaxially grown on the substrate, the first screen layer having a first dopant and a first dopant concentration;

a first channel layer epitaxially grown on the first screen layer, the first channel layer being undoped;

a second field effect transistor, the second field effect transistor comprising;

a second screen layer epitaxial grown on the substrate, the second screen layer having a second dopant and a second dopant concentration;

a second channel layer epitaxially grown on the second screen layer, the second channel layer being undoped; and

an isolation region separating the first field effect transistor from the second field effect transistor, the isolation region being formed after the formation of the first and second screen layers and first and second channel layers for the first and second field effect transistors;

wherein the first screen layer or the second screen layer has a lower junction leakage due to epitaxial growth than a comparable ion implanted screen layer.